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To fulfil the increasing requirements of electric/electronic architectures in automotive environments new concepts for future Electronic Control Units (ECU) are needed. Novel architectures offer much higher potential in terms of performance compared to higher clock rates in standard microcontroller devices. The following contribution discusses the performance benefits of new concepts as well as advantages in early development phases. We focus on two systems: A central body controller and a gateway system. Both are realized on reconfigurable hardware. In comparison to microcontrollers the FPGA technology offers the opportunity of task parallelization and partial dynamically reconfiguration. These novel architectures demand new tool flows and standards which will be also addressed in this paper.

Timing evaluation methods help to design a robust and extendible E/E architecture (electric/electronic). BMW has introduced the systematic application of such methods in the E/E design process within the last three years. Meanwhile, most of the architectural changes are now verified by a tool-based, automatic real-time analysis. This has increased the accuracy of the network planning and productivity of the BMW network department. In this paper, we give an overview of the actual status of timing evaluations in BMW's E/E architecture design. We discuss acceptance criteria, analysis metrics, and design rules, as far as these are related to timing. We look specifically at automation options, as these improve the productivity further. We will see that timing analysis has matured and should be mandatory for application in mass production E/E architecture development. At the same time, there is room for future improvements.

Autonomous driving systems and connected mobility are the next big developments for the car manufacturers and their suppliers during the next decade. To achieve the high computing power needs and fulfill new upcoming requirements due to functional safety and security, heterogeneous processor architectures with a mixture of different core architectures and hardware accelerators are necessary. To tackle this new type of hardware complexity and nevertheless stay within monetary constraints, high performance computers, inspired by state of the art data center hardware, could be adapted in order to fulfill automotive quality requirements. The European Processor Initiative (EPI) research project tries to come along with that challenge for next generation semiconductors. To be as close as possible to series development needs for the next upcoming car generations, we present a hybrid semiconductor system-on-chip architecture for automotive.

The increasing functionality and complexity of future electric/electronic architectures requires efficient methods and tools to support design decisions, which are taken in early development phases 6. For the past four years, a holistic approach for architecture development has been established at Mercedes-Benz Cars R&D department. At its core is a seamless design flow, including the conception, the analysis and the documentation for electric/electronic architectures. One of the actual challenges in the design of electric/electronic architectures concerns communication behavior and network topologies. The increasing data exchange between the ECUs creates high requirements for the networks. With the introduction of FlexRay 21 and Ethernet the automotive network architecture become a lot more heterogeneous. Especially gateways must fulfill many new requirements to handle the strict periodic schedule of FlexRay and the partly event-triggered communication on CAN-busses 23.