Search Results

This paper proposes a new development method for highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that allows the full simulation of the virtual mechanical control system including CPU and object code level software. In this paper, Renesas SH-2A microcontroller model was developed on CoMET™ platform from VaST Systems Technology. A ETC (Electronic Throttle Control) system and engine control system were chosen to prove this concept. The ETB (Electronic Throttle Body) model on Saber® simulator from Synopsys® or engine model on MATLAB®/Simulink® simulator from MathWorks can be simulated with the SH-2A model. To help the system design, debug and evaluation, we developed an integrated behavior analyzer, which can display CPU behavior graphically during the simulation without affecting the simulation result, such as task level CPU load, interrupt statistics, software variable transition chart, and so on.

As the demand for more complex system development and the ever-increasing requirement for improvement in software productivity, the need for graphical programming or Zero-Hand Coding for automatic generation of controller software becomes highly desirable. The graphical programming must not be limited to the algorithm development which consists of the application modules but must be extended to the microcontroller platform, which include the middleware (i.e. operating system, I/O device drivers) and hardware. Automatic code generation is very important for programming the complex microcontroller internal parameters and registers. The combined software tool chain is to generate the final target specific executable code. This approach is very beneficial for system development, reduction of the development cycle and bridges the gap between control and software engineers reducing time, effort and cost of the production software.

In the past few years, the demands for more complex system development and the ever-increasing requirement for hardware and software improvements have increased the need for a virtual embedded system where the hardware, microcontroller and software co-exist at the simulation level. This paper discusses the implementation of an approach that allows the full simulation of the embedded system. In the scope of this paper the definition of an embedded system refers to the electro-mechanical plant, the microcontroller, the peripherals and the software. The sensors and actuators are developed with a conservative type simulator such as Saber from Synopsys. The microcontroller and the attached peripherals are developed and modeled with the Comet environment from VaST. The microcontroller simulator is instruction cycle accurate. We are describing an innovative concept that will allow co-simulation between the two simulators.

In the past few years, the demand for more complex system development and the ever-increasing requirement for improvement in software productivity have amplified the need for graphical programming and automatic generation of controller software. This paper discusses the implementation of graphical code generation in the context of a fully automated calibratable system. Generally, controller parameters coarse tuning is done at the simulation level with a virtual plant and then fine-tuned when the code is downloaded onto the target controller. The tuning process is then based on trial and error approach relying on experienced calibrators to perform this tedious work. We are proposing an innovative concept that will automate the whole process of controller development. This process goes from the control algorithm code generation to the real-time calibration of the controller parameters on the actual target controller.

We have developed a full virtual engine system prototyping platform with 4-cylinder engine plant model, SH-2A CPU hardware model, and object code level software including OSEK OS. The virtual engine system prototyping platform can run simulation of an engine control system and digital knock detection system including 64-pt FFT computations that provide required high-resolution DSP capability for detection and control. To help the system design, debugging, and evaluation, the virtual system prototyping consists of behavior analyzer which can provide the visualization of useful CPU internal information for control algorithm tuning, RTOS optimization, and CPU architecture development. Thus the co-simulation enables time and cost saving at validation stage as validation can be performed at the design stage before production of actual components.