Design and Implementation of a Dual Processor Platform for Powertrain Systems 2000-01-C050
This paper describes a dual-processor platform for automotive powertrain control with a high-bandwidth interconnection network among processors, memory, and I/O sub-systems, which is suitable for a System-On-Chip (SOC) implementation. The two processors share memory and I/O address space and can operate in parallel at full speed. The cost of this solution, in terms of gates and power dissipation, is not substantially higher than more classical architectures with a multi-master bus or multiple processor busses connected through gateways, but offers almost twice the performance.
Alberto Ferrari, Sergio Garue, Maurizio Peri, Saverio Pezzini, Luca Valsecchi, Francesco Andretta, Walter Nesci
PARADES EEIG, ST Microelectronics, Magneti Marelli
Convergence 2000 International Congress on Transportation Electronics