A new central processing unit (CPU) architecture, which aimed at small size and high performance for the automotive control, is proposed. The features are 32-bit reduced instruction set computer (RISC), variable instruction length (16 and 32 bits), correction Harvard bus, and two-instruction simultaneous fetching (2 words fetch). An instruction set and a bus architecture are decided from results of statistically analyzing real programs for automotive controls. In addition, the performance of the CPU is enabled to the double of the access speed of the memory by the 2 words fetch architecture, without the cache organization. As the result, the area of the CPU is small with 1/3 and the performance realized the speedup of 20%, in comparison with conventional RISC (32-bit instruction length, Neumann bus, 1 word fetch, cache organization). Moreover, the guarantee of the indispensable real time for automotive control is also possible; because there is no lowering of the performance in cache miss.