Arc Fault Protection, Application Techniques for Aircraft Circuit Breakers 2006-01-2419
The military and commercial aerospace community has identified arcing faults as a major cause of damage to aircraft and danger to personnel. In some extreme cases, arcing is suspected of resulting in significant loss of life. Research and development activities at circuit breaker manufacturers like Sensata Technologies, as well as aircraft OEMs, airlines, the FAA, NAVAIR, and the US Air Force are confirming that a number of viable technologies exist with the capability to effectively distinguish between deleterious arcing events and normally operating aerospace systems. Low level arcing, below the rated load of some circuit breakers, has the potential to lead to system damage and has been effectively distinguished from normally operating aerospace systems.
The incorporation of the first SAE slash sheets to the already incorporated arc fault base specification AS5692 will be followed shortly by the first qualification of Arc Fault Circuit Breakers (AFCBs). This starts the process of learning how to apply and optimize arc fault protection in aerospace systems. This is the time to review and rationalize a number of design subtleties.
Exception handling techniques are one example of these subtleties. Whether designing with a RTCA/DO254 compliant hardware solution, or a RTCA/DO178 compliant software solution, it is important to design the appropriate exception responses into an AFCB. In some applications the appropriate response to a defined exception will be the suspension of arc detection protection. In other applications the appropriate response to a defined exception will be the removal of power from the protected circuit.
Dual indication is another such subtlety. In some applications the ability to differentiate between thermal trip and an arc detection trip will provide useful information. In other applications this feature is not only unnecessary; it can actually cause safety and cost issues.
This paper will outline some of the details associated with balancing exception responses as well as other design subtleties, such as dual indication and low-level detection, with application requirements.