Timing Analysis and Tracing Concepts for ECU Development 2014-01-0190
Integration scenarios for ECU software become more complicated, as more constraints with regards to timing, safety and security need to be considered. Multi-core microcontrollers offer even more hardware potential for integration scenarios. To tackle the complexity, more and more model based approaches are used.
Understanding the interaction between the different software components, not only from a functional but also from a timing view, is a key success factor for high integration scenarios.
In particular for multi-core systems, an amazing amount of timing data can be generated. Usually a multi-core system handles more software functionality than a single-core system. Furthermore, there may be timing interference on the multicore systems, due to the shared usage of buses, memory banks or other hardware resources. The current approach for timing analysis, often based on execution times and sequences of executions in Gantt charts, will not scale arbitrarily for high integration scenarios on multi-core systems.
This report introduces hardware support for non-intrusive tracing and a software analysis methodology with a focus on the analysis of multi-core software. Hence, race conditions and performance issues, often caused by access conflicts with buses or memories, can be investigated efficiently. Background for the constraints of non-intrusive tracing support on modern cost sensitive microcontrollers is given. Hardware support for non-intrusive tracing is not a new technology; it exists for several microcontrollers since years. However, it gains a lot of importance for multi-core systems. The developer needs to consider the complete system including buses and memories.