Browse Publications Technical Papers 2014-01-2176
2014-09-16

Verification, Validation and Uncertainty Quantification (VV&UQ) Framework Applicable to Power Electronics Systems 2014-01-2176

The development of the concepts, terminology and methodology of verification and validation is based on practical issues, not the philosophy of science. Different communities have tried to improve the existing terminology to one which is more comprehensible in their own field of study. All definitions follow the same concept, but they have been defined in a way to be most applicable to a specific field of study.
This paper proposes the Verification, Validation, and Uncertainty Quantification (VV&UQ) framework applicable to power electronic systems. Although the steps are similar to the VV&UQ frameworks' steps from other societies, this framework is more efficient as a result of the new arrangement of the steps which makes this procedure more comprehensible. This new arrangement gives this procedure the capability of improving the model in the most efficient way.
Since the main goal of the VV&UQ process is to quantitatively assess the confidence in modeling and simulation, the second part of this paper focuses on uncertainty quantification. This process is used to gather all uncertainties in the modeling and simulation, such as model form uncertainty, model inputs uncertainty, and uncertainty due to the numerical approximations, in order to quantitatively assess the reliability of the model. As an example, the reliability of the switching model of a three-phase voltage source inverter has been quantitatively assessed. The 3 kW three-phase voltage source inverter prototype has been conducted to set up validation experiments.

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