Testability measures the extent to which a system or unit supports fault detection and fault isolation in a confident, timely and cost-effective manner. The incorporation of adequate testability, including Built-In Test (BIT), requires early and systematic management attention to testability requirements, design and measurement. Whilst the design of BIT has become a standard design practice for a complex control system, the process to measure the effectiveness of such circuitry (both hardware and software) remains qualitative. The Built-In Test Effectivity Analysis (BEA) tries to quantify such analysis at each phase; identifying requirement gaps that help design safer products. The BEA modifies standard reliability programme to use Failure Modes and Effects and Criticality Analysis (FMECA), and reliability prediction of each functional group to generate a measure of how thoroughly the system can check itself. Initially discussed by Collet et al, this method is restricted by assumptions such as exclusion of generic faults and incorruptible BIT circuitry. This paper aims to optimize the present methodology by using a modified Failure Mode Effects Summary (FMES) template to identify and isolate faults that help determine hardware/software requirements that can mitigate BIT circuitry faults as well as generic failures.