Automated Assessment of E/E-Architecture Variants Using an Integrated Model- and Simulation-Based Approach 2019-01-0111

Due to the continuously increasing complexity of automotive electric/electronic architectures (EEAs), model-based systems engineering principles became state-of-the-art for designing such heterogeneous systems. However, current Architecture Description Languages (ADLs) as well as their system-design and analysis tools and frameworks for simulation-based analysis of EEA models often are not fully integrated in a single design process. They usually require error-prone import/export processes, especially when considering distributed collaboration, from EEA data models to external analysis frameworks and vice versa. Particularly, this limits the efficient assessment and comparison of distinct architecture variants regarding certain non-functional properties. Moreover, simulation-based analysis of the latter intended for EEA assessments in early concept phases demands backtracking capabilities to allow iterative model adaptations.

In this paper, a novel approach for evaluating EEAs dynamically regarding several metrics and comparing their architecture variants is presented. A generic concept to integrate actor-oriented simulation and analysis tools into EEA system-design tools is shown, based on a previously developed approach to synthesize and execute a cross-domain simulation model derived from static EEA descriptions designed in PREEvision. Additionally, the concept comprises the design model’s execution in a loop to allow iterative modifications of customer specific metrics as well as the automated assessment of their impact on the model. Furthermore, a variant-sensitive synthesis mode is introduced to analyze and compare distinct architecture variants. Therefore, intermediate simulation results and the Universally Unique Identifiers (UUIDs) of their source model artifacts are fed back and stored coherently in a simulation data registry. This facilitates to link the synthesized simulation model artifacts with the original EEA model artifacts and thus enables backtracking and the usage of the gained data in further analysis metrics. To proof this concept, the focus lies on the evaluation and comparison of two architecture variants, a centralized and a distributed hardware topology, in terms of the incurred CAN communication latencies of several activity chains and the resulting bus loads.