1995-02-01

Network I/O and System Considerations 950036

The J1850 bus requirements promote an unique and well characterized physical layer behavior developed through the learning curve of previous multiplex solutions. Design requirements such as: 1) Reliably interconnecting all of the vehicle's most complex modules, 2) Consistently withstanding the vehicle's harsh environment, and 3) Meeting SAE's functionality requirements, were all a formidable task to achieve. This paper will highlight the path taken to achieve a J1850 Bus interface which successfully met all of the design and functional goals. Chrysler's C2D insights will be discussed and related to goals for J1850. Other design considerations will also be discussed such as EMC issues, custom test equipment, and vehicle and component testability. In turn, silicon processes with special structures and topologies will be discussed relating the specific design with the needed electrical behavior. The HIP7020 J1850 BUS TRANSCEIVER I/O for MULTIPLEX WIRING accomplishes these requirements. This 8 pin SOIC and DIP is an integrated I/O bus transmitter/receiver designed for the SAE Standard J1850 Class B Data Communication Network physical interface.

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