Robert Bosch GmBH proposed in 2012 a new version of communication protocol named as Controller area network with Flexible Data-Rate (CANFD), that supports data frames up to 64 bytes compared to 8 bytes of CAN. With limited data frame size of CAN message, and it is impossible to be encrypted and secured. With this new feature of CAN FD, we propose a hardware design - CAN crypto FPGA chip to secure data transmitted through CAN FD bus by using AES-128 and SHA-1 algorithms with a symmetric key. AES-128 algorithm will provide confidentiality of CAN message and SHA-1 algorithm with a symmetric key (HMAC) will provide integrity and authentication of CAN message. The design has been modeled and verified by using Verilog HDL – a hardware description language, and implemented successfully into Xilinx FPGA chip by using simulation tool ISE (Xilinx).
To achieve high robustness and quality, automotive ECUs must initialize from low-power states as quickly as possible. However, microprocessor and memory advances have failed to keep pace with software image size growth in complex ECUs such as in Infotainment and Telematics. Loading the boot image from non-volatile storage to RAM and initializing the software can take a very long time to show the first screen and result in sluggish performance for a significant time thereafter which both degrade customer perceived quality. Designers of mobile devices such as portable phones, laptops, and tablets address this problem using Suspend mode whereby the main processor and peripheral devices are powered down during periods of inactivity, but memory contents are preserved by a small “self-refresh” current. When the device is turned back “on”, fully initialized memory content allows the system to initialize nearly instantaneously.