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In this paper, we present a project being conducted at Yalong Educational Equipment Company on control of educational robots using discrete event system theory. An educational robot is a programmable robot to be used by students for training and learning. To model a robot, we divide the robot into nine physical modules. Each module is modeled as an automaton. Parallel composition is used to obtain the entire model. The robot can be programmed to perform sequences of basic tasks. We investigate six basic tasks and use supervisors to control and achieve the tasks. Desired languages are obtained for all tasks and supervisory control theory is used to synthesize supervisors. To reduce computational complexity, modular/coordinated supervisors are used

This paper investigates the use of an adaptive proportional-integral-derivative (APID) controller to reduce a combustion engine crankshaft speed pulsation. Both computer simulations and engine test rig experiments are used to validate the proposed control scheme. The starter/alternator (S/A) is used as the actuator for engine speed control. The S/A is an induction machine. It produces a supplemental torque source to cancel out the fast engine torque variation. This machine is placed on the engine crankshaft. The impact of the slowly varying changes in engine operating conditions is accounted for by adjusting the APID controller parameters on-line. The APID control scheme tunes the PID controller parameters by using the theory of adaptive interaction. The tuning algorithm determines a set of PID parameters by minimizing an error function. The error function is a weighted combination of the plant states and the required control effort.

Microprocessors and microcontrollers are now widely used in automobiles. Microprocessor systems contain sources of interrupt and interrupt service routines, which are software components executed in response to the assertion of an interrupt in hardware. A major problem in designing the software of microprocessor systems is the analytical treatment of interrupt latency. Because multiple interrupt service routines are executed on the same CPU, they compete for the CPU and interfere with each other's latency requirements. Here, interrupt latency is defined as the delay between the assertion of the interrupt in hardware and the start of execution of the associated interrupt service routine. It is estimated that 80% of intermittent bugs in small microprocessor software loads are due to improper treatment of interrupts. Until this work, there is no analytic method for analyzing a particular system to determine if it may violate interrupt latency requirements.