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Cyber security is becoming increasingly critical in the car industry. Not only the entry points to the external world in the car need to be protected against potential attack, but also the on-board communication in the car require to be protected against attackers who may try to send unauthorized CAN messages. However, the current CAN network was not designed with security in mind. As a result, the extra measures have to be taken to address the key security properties of the secure CAN communication, including data integrity, authenticity, confidentiality and freshness. While integrity and authenticity can be achieved by using a relatively straightforward algorithms such as CMAC (Cipher-based Message Authentication Code) and Confidentiality can be handled by a symmetric encryption algorithm like AES128 (128-bit Advanced Encryption Standard), it has been recognized to be more challenging to achieve the freshness of CAN message.

With the introduction of the ISO26262 automotive safety standard there is a burden of proof to show that the processing elements in embedded microcontroller hardware are capable of supporting a certain diagnostic coverage level, depending on the required Automotive Safety Integrity Level (ASIL). The current mechanisms used to provide actual metrics of the Built-in Self Tests (BIST) and Lock Step comparators use Register Transfer Level (RTL) simulations of the internal processing elements which force faults into individual nodes of the design and collect diagnostic coverage results. Although this mechanism is robust, it can only be performed by semiconductor suppliers and is costly. This paper describes a new solution whereby the microcontroller is synthesized into a large Field Programmable Gate Array (FPGA) with a test controller on the outside.

As the automotive industry quickly moves towards hybridized and electrified vehicles, the optimal integration of power electronics in these vehicles will have a significant impact not only on the cost, performance, reliability, and durability; but ultimately on customer acceptance and market success of these technologies. If properly executed with the right cost, performance, reliability and durability, then both the industry and the consumer will benefit. It is because of these interdependencies that the pace and scale of success, will hinge on effective collaboration. This collaboration will be built around the convergence of automotive and industrial technology. Where real time embedded controls mixes with high power and voltage levels. The industry has already seen several successful collaborations adapting power electronics to the automotive space in target vehicles.

Infineon proposes a Quasi-Autonomous Gate Driver (QAGD) to manage an electrically actuated component, whether electromechanical, electromagnetic, or electrohydraulic. This paper examines some current control strategies that can be implemented within the QAGD, such as: Synchronous Sampling (SYSA), Hysteresis, Improved Synchronous Sampling-Hysteresis (ISSH), Suboscillation, Suboscillation with Back EMF Feedforward (SBEF) and Synchronous Control in Rotation Coordinates (SCRC). Analysis and simulation of these strategies indicate their advantages and disadvantages, which are then summarized in a comparison chart, from which the best solution for a given application can be determined. The QAGD IC proposed by Infineon adopts this solution by integrating the current controller and the driver unit for the MOSFETs in a single package. The inverter function can therefore be implemented using one QAGD and several MOSFETs, which greatly simplify the system and decrease the costs.

Today's requirements for engine management controllers are increasing in various aspects. Stronger emission standards and diagnosis requirements demand more complex control algorithms, faster system response times, better usage of sensor information throughout the system and higher accuracy of actuator stimuli. Despite that, new solutions are needed to answer the requirement for higher cost effectiveness, flexibility and reusability. The trade-off between cost and functionality is constantly being reviewed when choosing the right microcontroller to operate with an ECU. Integration of more complex and flexible functionality into the microcontroller helps to reduce the need for custom ASICs and thus reduce the overall system cost. In order to reduce the demands on CPU throughput within the microcontroller, manufacturers have introduced smart peripherals that off-load some of the work of the CPU into the peripherals.

Recent trends in field bus applications, especially in the automotive section, show a very high demand for data exchange between decentralised, intelligent functional units and modules. These functional units can be grouped together to power train applications or body/convenience applications. In many cases, the coupling of local modules is done with one or more independent bus systems. The actual design and the partitioning of the modules strongly depend on application-specific requirements, such as the total amount of data to be transferred or the maximum of the tolerated latency in data delivery. A very powerful and fast field bus is the CAN bus (Controller Area Network), which supports transfers with data rates up to 1 Mbits/s. Due to the higher transmission speed and the standardized functionality, CAN is a very interesting alternative to and improvement on bus systems based on other protocols.

The demands of the automotive market are decreasing the time-to-market required from the initial concept of new control systems to their implementation. The goal of automotive companies is to constantly reduce the development time to reap the full economic and strategic benefits of being quicker to market. The target is to reach a development time of less than 12 months for some applications. At the same time, the complexity of these new systems is growing almost exponentially. While new techniques like model-based control design with executable specifications, rapid control prototyping and hardware-in-the-loop simulation have helped significantly streamline the development process, the new strategies are still being transferred to the production target by hand. During an early project phase, automotive customers also need to explore different silicon architectures provided by semiconductor manufacturers to select the vendors who can offer the best solution at the lowest price.

The increasing legal requirements for safety, emission reduction, fuel economy and onboard diagnostic systems are forcing the market to increase complexity. This complexity must not be a reason for slowing down the introduction of new systems. For efficiency, car manufacturers and system suppliers want to focus on their core competencies and leave the micro-controller complexity to silicon vendors. Competition forces system suppliers to jump to the most “function/cost” effective solution. For this reason it is very dangerous to move in the direction of specific solutions which require a large amount of effort to modify. Therefore the market goes in the direction of standards with clear interfaces. The approach presented overcomes these obstacles by introducing a Configurable I/O System (CIOS) layer. The CIOS encompasses basic software driver objects for engine management systems encapsulating the standard sensors and actuators.

This paper describes the first single-core 32-bit microcontroller-DSP architecture, TriCore, optimized for real-time embedded systems, an OSEK/VDX Real-Time Operating System (RTOS) and an open, integrated development tools platform to allow a development downflow for high-level Computer Aided Software Engineering (CASE) design entry and simulation/validation, rapid prototyping down to the target hardware for calibration and debugging and the up-flow by feeding the data collected from the target Electronic Control Unit (ECU) for system analysis and debugging all the way back to the entry CASE level. Also described are the different features of the new 32-Bit microcontroller-DSP, which speeds up the execution of embedded control applications and simultaneously reduce memory demand.