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Technical Paper

Evaluation of Parallel Executions on Multiple Virtual ECU Systems

2018-04-03
2018-01-0011
We have developed a cooperative simulation environment for multiple electronic control units (ECUs) including a parallel executions mechanism to improve the test efficiency of a system, which was designed with multiple ECUs for autonomous driving. And we have applied it to a power window system for multiple ECUs with a controller area network (CAN). The power window model consists of an electronic-mechanical model and a CPU model. Each simulator with a different executions speed operates in parallel using a synchronization mechanism that exchanges data outputted from each simulator at a constant cycle. A virtual ECU simulated microcontroller hardware operations and executed its control program step-by-step in binary code to test software for the product version. As co-simulation technology, a mechanism that synchronously executes heterogeneous simulators and a model of an in-vehicle communication CAN connecting each ECU were developed.
Technical Paper

Virtual FMEA and Its Application to Software Verification of Electric Power Steering System

2017-03-28
2017-01-0066
This paper presents the “Virtual Failure Mode and Effects Analysis (vFMEA)” system, which is a high-fidelity electrical-failure-simulation platform, and applies it to the software verification of an electric power steering (EPS) system. The vFMEA system enables engineers to dynamically inject a drift fault into a circuit model of the electronic control unit (ECU) of an EPS system, to analyze system-level failure effects, and to verify software-implemented safety mechanisms, which consequently reduces both cost and time of development. The vFMEA system can verify test cases that cannot be verified using an actual ECU and can improve test coverage as well. It consists of a cycle-accurate microcontroller model with mass-production software implemented in binary format, analog and digital circuit models, mechanical models, and a state-triggered fault-injection mechanism.
Technical Paper

Virtual FMEA : Simulation-Based ECU Electrical Failure Mode and Effects Analysis

2014-04-01
2014-01-0205
“Virtual Failure Mode and Effects Analysis” (vFMEA), a novel safety-verification method of control software for automotive electronic systems, was proposed to save prototyping cost at verification stage. The proposed vFMEA is system-level FMEA method, which uses virtualized electronic control units (ECUs) consisting of microcontroller models on a microcontroller simulator and a transistor-level circuit models on a circuit simulator. By using the structure, the control software in binary code formats can be verified when a circuit-level fault occurs in the ECU hardware. As an illustrative example, vFMEA was applied to an engine ECU. As a result of short-circuit fault into a driver IC, engine revolution and engine speed decreased. However, the engine continued to operate normally when an open-circuit fault occurred in a capacitor connected in parallel. Effects of the hardware faults in ECU on a vehicle are demonstrated; thereby software verification can be performed using vFMEA system.
Journal Article

Virtual Engine System Prototyping with High-Resolution FFT for Digital Knock Detection Using CPU Model-Based Hardware/Software Co-simulation

2009-04-20
2009-01-0532
We have developed a full virtual engine system prototyping platform with 4-cylinder engine plant model, SH-2A CPU hardware model, and object code level software including OSEK OS. The virtual engine system prototyping platform can run simulation of an engine control system and digital knock detection system including 64-pt FFT computations that provide required high-resolution DSP capability for detection and control. To help the system design, debugging, and evaluation, the virtual system prototyping consists of behavior analyzer which can provide the visualization of useful CPU internal information for control algorithm tuning, RTOS optimization, and CPU architecture development. Thus the co-simulation enables time and cost saving at validation stage as validation can be performed at the design stage before production of actual components.
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