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Vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications are gaining increasing importance in automotive research and engineering domains. The novel communication scheme is targeted to improve driver safety (e.g., forward collision warnings) and comfort (e.g., routing to avoid congestion, automatic toll collection, etc.). Features exploiting these communication schemes are still in the early stages of research and development. However, growing attention to system wide infrastructure - in terms of OEM collaboration on interface standardization, protocol standardization, and government supported road/wireless infrastructure - will lead to popularity of such features in the future. This paper focuses on evaluating reliability and safety/integrity of data communicated over the wireless channels for early design verification. Analysis of a design can be done based on formal models, simulation, emulation, and testing.

To cope with the increasing number of advanced features (e.g., smart-phone integration and side-blind zone alert.) being deployed in vehicles, automotive manufacturers are designing flexible hardware architectures which can accommodate increasing feature content with as fewer as possible hardware changes so as to keep future costs down. In this paper, we propose a formal and quantitative definition of flexibility, a related methodology and a tool flow aimed at maximizing the flexibility of an automotive hardware architecture with respect to the features that are of greater importance to the designer. We define flexibility as the ability of an architecture to accommodate future changes in features with no changes in hardware (no addition/replacement of processors, buses, or memories). We utilize an optimization framework based on mixed integer linear programming (MILP) which computes the flexibility of the architecture while guaranteeing performance and safety requirements.

Recent trends in the automotive industry show growing demands for the introduction of new in-vehicle features (e.g., smart-phone integration, adaptive cruise control, etc.) at increasing rates and with reduced time-to-market. New technological developments (e.g., in-vehicle Ethernet, multi-core technologies, AUTOSAR standardized software architectures, smart video and radar sensors, etc.) provide opportunities as well as challenges to automotive designers for introducing and implementing new features at lower costs, and with increased safety and security. As a result, the design of Electrical/Electronic (E/E) architectures is becoming increasingly challenging as several hardware resources are needed. In our earlier work, we have provided top-level definitions for three relevant metrics that can be used to evaluate E/E architecture alternatives in the early stages of the design process: flexibility, scalability and expandability.

Given the fast changing market demands, the growing complexity of features, the shorter time to market, and the design/development constraints, the need for efficient and effective verification and validation methods are becoming critical for vehicle manufacturers and suppliers. One such example is fault-tree analysis. While fault-tree analysis is an important hazard analysis/verification activity, the current process of translating design details (e.g., system level and software level) is manual. Current experience indicates that fault tree analysis involves both creative deductive thinking and more mechanical steps, which typically involve instantiating gates and events in fault trees following fixed patterns. Specifically for software fault tree analysis, a number of the development steps typically involve instantiating fixed patterns of gates and events based upon the structure of the code. In this work, we investigate a methodology to translate software programs to fault trees.

Automotive HW/SW architectures are becoming increasingly complex to support the deployment of new safety, comfort, and energy-efficiency features. Such architectures include several software tasks (100+), messages (1000+), computational and communication resources (70+ CPUs, 10+ buses), and (smart) sensors and actuators (20+). To cope with the increasing system complexity at lowest development and product costs, highest safety, and fastest time to market, model-based rapid-prototyping development processes are essential. The processes, coupled with optimization steps aimed at reducing the number of software and hardware resources while satisfying the safety requirements, enable reduction of the system complexity and ease downstream testing/validation efforts. This paper describes a novel model-based design exploration and optimization process for the deployment of a set of software tasks on a dual-processor control module implementing a fail-safe strategy.