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Seven encapsulants with operating temperatures up to 250°C were surveyed for use in planar packages for wide-bandgap dice. Two of the encapsulants failed processability test because they were not able to flow, and another two failed because they induced voids or cracks after curing. The dielectric results of the remaining three encapsulants showed that both dielectric strength and permittivity decreased almost 40% when the temperature was increased up to 250°C. As the three encapsulants were used to encapsulate a power module, it was proven that all of them could protect the package from early breakdown caused by the poor dielectric strength of air.

Nano-silver sintered bonding was carried out at 275°C and under 3MPa pressures, and soldering in a vacuum reflowing oven to reduce voiding. Both joints are subject to large shear stresses due to the mismatch in coefficients of thermal expansion (CTE) between the chip and the substrate. In this study, residual stresses in the chip-on-substrate assemblies were determined by measuring the bending curvatures of the bonded structures. An in-house optical setup measured the bending curvatures using a thin-film stress measurement technique. From the measured bending curvatures and the mechanical properties of the constituent materials, residual stresses were calculated. The thermo-mechanical reliabilities of both joining techniques were tested by thermal cycling. The chip assemblies were cycled between -40°C and 125°C (100 minutes of cycle time, 10 minutes of dwell time) and the changes in their bending curvatures were measured.