Verification, Validation and Uncertainty Quantification (VV&UQ) Framework Applicable to Power Electronics Systems
The development of the concepts, terminology and methodology of verification and validation is based on practical issues, not the philosophy of science. Different communities have tried to improve the existing terminology to one which is more comprehensible in their own field of study. All definitions follow the same concept, but they have been defined in a way to be most applicable to a specific field of study. This paper proposes the Verification, Validation, and Uncertainty Quantification (VV&UQ) framework applicable to power electronic systems. Although the steps are similar to the VV&UQ frameworks' steps from other societies, this framework is more efficient as a result of the new arrangement of the steps which makes this procedure more comprehensible. This new arrangement gives this procedure the capability of improving the model in the most efficient way.