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Fault-Tree Generation for Embedded Software Implementing Dual-Path Checking

Given the fast changing market demands, the growing complexity of features, the shorter time to market, and the design/development constraints, the need for efficient and effective verification and validation methods are becoming critical for vehicle manufacturers and suppliers. One such example is fault-tree analysis. While fault-tree analysis is an important hazard analysis/verification activity, the current process of translating design details (e.g., system level and software level) is manual. Current experience indicates that fault tree analysis involves both creative deductive thinking and more mechanical steps, which typically involve instantiating gates and events in fault trees following fixed patterns. Specifically for software fault tree analysis, a number of the development steps typically involve instantiating fixed patterns of gates and events based upon the structure of the code. In this work, we investigate a methodology to translate software programs to fault trees.
Technical Paper

The Virtual Instrument Revolution

Empowering the end-user is the primary focus of most software developers, whether in the general computing industry or in automotive instrumentation applications. End-users' expectations for both ease of use and flexibility in software products are high. Products in the general computing industry, such as Microsoft Word and Excel, have set standards for what a user expects from a software product. Because of the complex nature of most analytical instrumentation applications, it is difficult to deliver a software product for these applications that is both easy to use and flexible for many applications. And, if the product does exist, it usually comes with a relatively high price tag. There are, however, some lower cost software development tools available for instrumentation applications that combine a good mix of flexibility and ease of use. These tools require some development on the part of the end-user, but they do not require a computer science background.
Technical Paper

Customizing a PXI-based Hardware-In-The-Loop Test System with LabVIEW

Hardware-in-the-loop (HIL) simulation has become standard practice in the verification process of electronic control units (ECUs). However, new system control concepts continue to drive and expand the requirements for HIL systems. In this maturing application space, there is a natural trend towards the use of commercial-off-the-shelf (COTS) tools and open, multivendor hardware architectures. This open architecture is critical in helping HIL testers meet these requirements in an increasingly cost effective and higher performance manner. Multicore processors today offer performance and flexibility on a scalable computing platform, which furthers this COTS trend. Computer platforms like desktop PCs, CompactPCI and PXI [ 1 ] (CompactPCI eXtensions for Instrumentation) deliver high-performance systems that allow for the leveraging of multicore processor capabilities in achieving highly realistic plant simulations for controller testing.
Technical Paper

GPS Synchronization Architecture for Dynamic Signal Acquisition

In many measurement applications, there is a need to correlate data acquired from different systems or synchronize systems together with precise timing. Signal Based and Time Based are the two basic methods of synchronizing instrumentation. In Signal Based synchronization, clocks and triggers are physically connected between systems. Typically this provides the highest precision synchronization. In many NVH applications size and distance constrains physically connecting the systems needed for making measurements though the inter-channel phase information of simultaneously sampled signals is crucial. In Time Based synchronization, system components have a common reference of what time it is. Events, triggers and clocks can be generated based on this time.
Technical Paper

Advanced Signal Processing Algorithms for Sound and Vibration Beyond the FFT

Several advanced signal processing algorithms beyond the FFT such as time-frequency analysis, quefrency, cestrum, wavelet analysis, and AR modeling uses are outlined. These advanced algorithms can solve some sound and vibration challenges that FFT-based algorithms cannot solve. Looking at signal characteristics of a unit under test in the time-frequency plane, it is possible to get a better understanding of signal characteristics. This is an overview of these algorithms and some application examples, such as speaker testing, bearing fault detection, dashboard motor testing, and engine knock detection where they can be applied to NVH applications.
Technical Paper

Making the Most of Your Test Systems with Proper Data Storage Techniques

Companies typically invest significant time and money in choosing the proper test equipment for new automotive test systems. Yet, the architecture for proper data storage and management of the mounds of data these systems produce is often times an afterthought. Although data management may not appear as an obstacle during initial design, as the system expands, changes, and interfaces with other systems, the ability to easily access and exchange technical data becomes a critical challenge to overcome. This paper will introduce new technologies giving engineers the power to search and mine data sets to find key information and trends in the data for to rapidly turn the raw data into results.
Technical Paper

Methods and Tools for End-to-End Latency Analysis and Optimization of a Dual-Processor Control Module

Automotive HW/SW architectures are becoming increasingly complex to support the deployment of new safety, comfort, and energy-efficiency features. Such architectures include several software tasks (100+), messages (1000+), computational and communication resources (70+ CPUs, 10+ buses), and (smart) sensors and actuators (20+). To cope with the increasing system complexity at lowest development and product costs, highest safety, and fastest time to market, model-based rapid-prototyping development processes are essential. The processes, coupled with optimization steps aimed at reducing the number of software and hardware resources while satisfying the safety requirements, enable reduction of the system complexity and ease downstream testing/validation efforts. This paper describes a novel model-based design exploration and optimization process for the deployment of a set of software tasks on a dual-processor control module implementing a fail-safe strategy.
Technical Paper

Development of a Large-Scale Microphone Array for Aircraft Jet Plume Noise Source Characterization

Military jet aircraft expose both ground maintenance personnel and the community to high levels of noise. The U.S. Department of Defense is funding research to develop advanced modeling tools for noise reduction techniques and community noise exposure. A large-scale microphone array for portable near-field acoustic holography (NAH) and data acquisition system was created for this purpose. The system was designed for measuring high-amplitude jet noise from current and next-generation military aircraft to provide model refinement and benchmarking, evaluate performance of noise control devices, and predict ground maintenance personnel and community noise exposure. The acoustical instrumentation system was designed to be easy to use with scalable data processing as the primary focus. The data acquisition system allowed up to 152 channels simultaneously sampled at a rate of 96 kHz.
Technical Paper

Addressing Engine ECU Testing Challenges with FPGA-Based Engine Simulation

Engine ECU testing requires sophisticated sensor simulation and event capture equipment. FPGAs are the ideal devices to address these requirements. Their high performance and high flexibility are perfectly suited to the rapidly changing test needs of today's advanced ECUs. FPGAs offer significant advantages such as parallel processing, design scalability, ultra-fast pin-to-pin response time, design portability, and lifetime upgradability. All of these benefits are highly valuable when validating constantly bigger embedded software in shorter duration. This paper discusses the collaboration between Valeo and NI to define, implement, and deploy a graphical, open-source, FPGA-based engine simulation library for ECU verification.
Technical Paper

Development of a Portable Acoustic Beamformer using FPGA Technology and Digital Microphones

This is an overview of the development of a portable, real-time acoustic beamformer based on FPGA (Field Programmable Gate Arrays) and digital microphones for noise source identification. Microphone arrays can be a useful tool in identifying noise sources and give designers an image of noise distribution. The beamforming algorithm is a classic and efficient algorithm for signal processing of microphone arrays and is the core of many microphone array systems. High-speed real-time beamforming has not been implemented much in a portable instrument because it requires large computational resources. Utilizing a beamforming algorithm running on a Field Programmable Gate Array (FPGA), this camera is able to detect and locate both stationary and moving noise sources. A high-resolution optical camera located in the middle of the device records images at a rate of 25 frames per second. The use of the FPGA technology and digital microphones provides increased performance, reduced cost and weight.
Technical Paper

Simulation of LIN Clusters for Reducing In-Vehicle Network Development and Validation Costs

LIN is a low-cost, low-speed vehicle communication sub-bus becoming increasingly pervasive in automotive subsystems. It is a simple, UART-based master-slave protocol designed as a low-speed supplement to a CAN or FlexRay bus. Its primary application is cabin comfort and human interface hardware such as dashboard controls, power seat harnesses, and power door/window systems. As automotive network designers attempt to reduce wiring complexity and lower system cost, modular, inexpensive sub-buses like LIN become an attractive option. This paper presents an overview of the LIN standard and its applications, and then proposes an architecture for rapid development of LIN networks via hardware simulations of LIN nodes. Using inexpensive, off-the-shelf hardware, LIN sensor and actuator applications can be tested in-place without microcode development, speeding overall network development time.
Technical Paper

Understanding the PC Technologies that Can Make or Break Modern Noise and Vibration Instrumentation Systems

Almost every automotive noise, vibration, and harshness (NVH) engineer who has ever looked at a fast Fourier transform knows the difference between instruments with 90 dB and instruments with 120 dB of dynamic range. NVH engineers understand instrumentation specs such as 24-bit resolution analog-to-digital converters and alias-free signal bandwidth. However, with modern noise and vibration instrumentation systems now being almost completely built on the PC, these specs neglect the most important X factor: the PC itself. No other aspect can affect the performance of an instrumentation system for a sensor array more than the components of the PC. Fortunately, a variety of off-the-shelf PC technologies built on industry standards are available to make it easier and less expensive than ever before to instrument and manage data from large systems. But an NVH engineer must wade through a sea of options to choose the right PC technologies for desired instrumentation system performance.
Technical Paper

High Channel Count Systems Architecture for Noise and Vibration Measurements

Modular instrumentation is being widely used in noise and vibration measurement systems that demand higher channel counts and the wider dynamic range that 24-bit delta-sigma ADCs make available at lower costs. This is an overview how flexible modular instrumentation employing the latest software technology can be used in making high precision noise and vibration measurements where higher sampling rates, higher channel counts, increased dynamic range, and distributed architectures were needed in smaller packages. An example where this is being used is in acoustic beam forming in aircraft pass by noise tests to measure and distinguish engine and airframe noise sources.
Technical Paper

Tool Integration from Design to Test

The increasing number of features and complexity of today's automotive software architectures bring new challenges to the product development cycle. As a product is being developed, there is a need for information created during the early phases to flow seamlessly into subsequent phases. For example, information defined for an ECU during the design phase should be re-used when that ECU is tested during manufacture. Challenges often arise from the fact that one vendor's tools may be appropriate for design, but a different vendor's tools are best suited for manufacturing test. This paper discusses business and technical issues surrounding the transfer of information between such tools. Two case studies are used for discussion. One deals with databases describing signals transferred over an in-vehicle network and the other discusses simulation models as both transition from early designs through various test phases.
Technical Paper

A PC and FPGA Hybrid Approach to Hardware-in-the-Loop Simulation

ECU designers are seeking more flexibility from HIL test systems. Often their needs are met by the development of custom hardware, either internally or by HIL test system vendors. Many systems also rely heavily on the use of multiple expensive microprocessors to achieve the required timing and synchronization performance. This paper discusses an alternative based on PC technology and reconfigurable I/O hardware. The HIL test system designer uses a graphical programming interface to reconfigure not only the real-time software portion of the system, but also the FPGA-based I/O hardware. This increases flexibility and lowers cost by providing capabilities such as generating simulated outputs synchronized to crank angle and implementing multiple serial communication protocols.
Technical Paper

Hardware Synchronization Techniques of Analog, Digital, and CAN Signals for Device Validation

With the abundance of electronic devices and sensors in automotive technology, it has become increasingly important to establish efficient, cost-effective device validation methods for CAN, J1939, and GMLAN. An easy method of validation is simultaneous sampling of multiple measurements for comparison. For instance, if you have an ECU that receives inputs using CAN, and controls analog outputs, you can measure both CAN and analog data to verify that the ECU algorithm is behaving properly. This paper will discuss techniques for sharing timing and triggering signals between CAN, analog, and digital hardware to prevent clock drift and start latencies and reduce operating system jitter. We will cover techniques to use a common clock to drive multiple boards and specify events to trigger multiple board acquisitions. Timing and triggering signals can be shared in a PC through timing and triggering cables or in PXI through the PXI Trigger bus in the backplane.
Technical Paper

Using Finite-Element Analysis Results and Field-Programmable Gate Arrays to Accelerate Hybrid Powertrain Controller Validation

Test and validation of control systems for hybrid vehicle power trains provide a unique set of challenges. Not only does the electronic control unit (ECU), or pair of ECUs, need to smoothly coordinate power flow between two or more power plants, but it also must handle the power electronics' high-speed dynamics due to PWM signals frequently in the 10-20 kHz range. The trend in testing all-electric and hybrid-electric ECUs has moved toward using field-programmable gate arrays (FPGAs) as the processing node for simulating inverter and electric motor dynamics in real time. Acting as a purpose-built processor colocated with analog and digital input and output, the FPGA makes it possible for real-time simulation loop rates on the order of one microsecond.
Journal Article

Methods and Tools for Calculating the Flexibility of Automotive HW/SW Architectures

To cope with the increasing number of advanced features (e.g., smart-phone integration and side-blind zone alert.) being deployed in vehicles, automotive manufacturers are designing flexible hardware architectures which can accommodate increasing feature content with as fewer as possible hardware changes so as to keep future costs down. In this paper, we propose a formal and quantitative definition of flexibility, a related methodology and a tool flow aimed at maximizing the flexibility of an automotive hardware architecture with respect to the features that are of greater importance to the designer. We define flexibility as the ability of an architecture to accommodate future changes in features with no changes in hardware (no addition/replacement of processors, buses, or memories). We utilize an optimization framework based on mixed integer linear programming (MILP) which computes the flexibility of the architecture while guaranteeing performance and safety requirements.
Journal Article

Exploring Use of Ethernet for In-Vehicle Control Applications: AFDX, TTEthernet, EtherCAT, and AVB

Vehicle communication networks are challenged by increasing demands for bandwidth, safety, and security. New data is coming into the vehicle from personal devices (e.g. mobile phones), infotainment systems, camera-based driver assistance, and wireless communication with other vehicles and infrastructure. Ethernet (IEEE 802.3) provides high levels of bandwidth and security, making it a potential solution to the challenges of vehicle communication networks. However, in order to be used in control applications, Ethernet must provide known timing performance (e.g. bounded latency and jitter), and in some cases redundancy. This paper explores use of Ethernet for in-vehicle control applications.
Technical Paper

Adding Unified Diagnostic Services over CAN to an HIL Test System

The increase in the number of electronic control units (ECUs) in the modern vehicle, combined with increased software complexity and more distributed controls has led to an extreme testing challenge when it comes to the verification and validation of body-control ECUs. In general test engineers have to deal with more software configurations, more closed-loop interaction between ECUs, and more fault conditions than ever before. By adding Unified Diagnostic Services (UDS) over CAN to a Hardware-In-The-Loop (HIL) test system, Lear was able to increase test automation and provide wider test coverage by automating the ECU flashing process, adding diagnostic identifiers and trouble codes to their test scripts, and providing a quick and easy way to exercise ECU I/O. Lear chose to implement their HIL testers on the open PXI[1] hardware platform, utilizing National Instruments' VeriStand software framework.