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Technical Paper

Integrated Electrical System Testing and Modeling for Risk Mitigation

2008-11-11
2008-01-2897
International Space Station (ISS) Payload Engineering Integration (PEI) organization adopted the advanced computation and simulation technology to develop integrated electrical system models based on the test data of various sub-units. This system model was used end-to-end to mitigate system risk for the integrated Space Shuttle Pre-launch and Landing configurations. The Space Shuttle carries the Multi-Purpose Logistics Module (MPLM), a pressurize transportation carrier, and the Laboratory Freezer for ISS, a freezer rack for storage and transport of science experiments from/to the ISS, is carried inside the MPLM. An end-to-end electrical system model for Space Shuttle Pre-Launch and Landing configurations, including the MPLM and Freezer, provided vital information for integrated electrical testing and to assess Mission success. The Pre-Launch and Landing configurations have different power supplies and cables to provide the power for the MPLM and the Freezer.
Technical Paper

Dynamic Circuit Analysis and Testing for International Space Station Science Experiments

2008-11-11
2008-01-2911
The International Space Station (ISS) Payload Engineering Integration (PEI) organization has developed the critical capabilities in dynamic circuit modeling and simulation to analyze electrical system anomalies during testing and operation. This presentation provides an example of the processes, tools and analytical techniques applied to the improvement of science experiments over-voltage clamp circuit design which is widely used by ISS science experiments. The voltage clamp circuit of Science Rack exhibits parasitic oscillations when a voltage spike couples to the Field-Effect Transistor (FET) in the clamp circuit. The oscillation can cause partial or full conduction of the shunt FET in the circuit and may result in the destruction of the FET. In addition, the voltage clamp circuit is not designed to detect the high current through the FET, and this condition can result in damage to surrounding devices. These abnormal operations were analyzed by dynamic circuit simulation and tests.
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