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Technical Paper

A Novel Beamspace Technology Based On 2FCW for Radar Target Detection

2017-03-28
2017-01-0025
In the last decade, radar-based Advanced Driver Assistance Systems (ADAS) have improved safety of transportation. Today, the standardization of ADAS established by New Car Assessment Program (NCAP) is expected to expand its market globally. One of the key technologies of ADAS is the rear-side monitoring system such as Blind Spot Warning (BSW) and Closing Vehicle Warning (CVW). It is required to expand its detection range so that it can monitor not only nearside targets for BSW, but farther targets for CVW. These applications can be achieved using two radar sensors installed at rear-side corner of the vehicle. However, the expanded detection range causes undesirable target detections and decreases target recognition performance. In this paper, a novel solution to improve the performance using DCMP(Directional-Constrained Minimization of Power)-based Beamspace technology using Two-frequency continuous wave (2FCW also known as FSK) is introduced.
Technical Paper

Virtualization Technology and Using Virtual CPU in the Context of ISO26262: The E-Gas Case Study

2013-04-08
2013-01-0196
A new development environment is required where conflict between control systems is minimized, where processing can be executed while maintaining independence between systems, and where quality can be assured easily. This environment must enable flexibility in software layouts to accommodate software changes during the development process and the parallel development of multiple derivative systems. We have developed virtualization technology (virtual CPU), which allows the execution of system control with a single CPU without conflict between systems. An outstanding virtual CPU architecture that we have developed allows us to execute multiple real-time control tasks with the hardware scheduler, and we have developed hardware that extends the management of address space and interrupt handling, making it possible for a single CPU to be configured as multiple CPUs. Also, we have implemented a bus system that reduces interference between threads.
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