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Robert Bosch GmBH proposed in 2012 a new version of communication protocol named as Controller area network with Flexible Data-Rate (CANFD), that supports data frames up to 64 bytes compared to 8 bytes of CAN. With limited data frame size of CAN message, and it is impossible to be encrypted and secured. With this new feature of CAN FD, we propose a hardware design - CAN crypto FPGA chip to secure data transmitted through CAN FD bus by using AES-128 and SHA-1 algorithms with a symmetric key. AES-128 algorithm will provide confidentiality of CAN message and SHA-1 algorithm with a symmetric key (HMAC) will provide integrity and authentication of CAN message. The design has been modeled and verified by using Verilog HDL – a hardware description language, and implemented successfully into Xilinx FPGA chip by using simulation tool ISE (Xilinx).

The Controller Area Network (CAN) provides the user with several parameters to configure the bit timing, sampling point, and bit rate. With this flexibility comes some complexity in choosing the correct values for these parameters and properly configuring the bit rate. A given bit rate can be achieved by setting these parameter in more than one way. It is also possible to incorrectly configure these parameters and achieve a close enough bit rate that will allow the system to function but not perform in an optimized manner. This paper discusses how to calculate the bit rate and how to choose some of these parameters. A set of equations were developed and used in an example to configure the bit rate for a PIC18FXX8 CAN controller.