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Experimental Hardware-in-the-loop (xHIL) testing utilizing signal and/or power emulation imposes a hard real-time requirement on models of emulated subsystems, directly limiting their fidelity to what can be achieved in real-time on the available computational resources. Most real-time simulators are CPU-based, for which the overhead of an instruction-set architecture imposes a lower limit on the simulation step size, resulting in limited model bandwidth. For power-electronic systems with high-frequency switching, this limit often necessitates using average-value models, significantly reducing fidelity, in order to meet the real-time requirement. An alternative approach emerging recently is to use FPGAs as the computational platform, which, although offering orders-of-magnitudes faster execution due to their parallel architecture, they are more difficult to program and their limited fabric space bounds the size of models that can be simulated.