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Standard

Digital Time Division Command/Response Multiplex Data Bus

1995-11-01
HISTORICAL
AS15531
This SAE Aerospace Standard (AS) contains requirements for a digital time division command/response multiplex data bus, for use in systems integration, that is functionally equivalent to MIL-STD-1553B with Notice 2. Even with the use of this document, differences may exist between multiplex data buses in different system applications due to particular application requirements and the options allowed in this document. The system designer must recognize this fact and design the multiplex bus controller (BC) hardware and software to accommodate such differences. These designer selected options must exist to allow the necessary flexibility in the design of specific multiplex systems in order to provide for the control mechanism, architectural redundancy, degradation concept, and traffic patterns peculiar to the specific application requirements.
Standard

Digital Time Division Command/Response Multiplex Data Bus

2017-03-21
CURRENT
AS15531A
This SAE Aerospace Standard (AS) contains requirements for a digital time division command/response multiplex data bus, for use in systems integration, that is functionally equivalent to MIL-STD-1553B with Notice 2. Even with the use of this document, differences may exist between multiplex data buses in different system applications due to particular application requirements and the options allowed in this document. The system designer must recognize this fact and design the multiplex bus controller (BC) hardware and software to accommodate such differences. These designer selected options must exist to allow the necessary flexibility in the design of specific multiplex systems in order to provide for the control mechanism, architectural redundancy, degradation concept, and traffic patterns peculiar to the specific application requirements.
Standard

Handbook for the Digital Time Division Command/Response Multiplex Data Bus Test Plans

2016-10-21
CURRENT
AIR4295A
This document contains guidance for using SAE publications, AS4112 through AS4117 (MIL-STD-1553 related Test Plans). Included herein are the referenced test plan paragraphs numbers and titles, the purpose of the test, the associated MIL-STD-1553 paragraph, commentary concerning test methods and rationale, and instrumentation requirements.
Standard

High Performance 1553 Research and Development

2016-10-21
CURRENT
AIR5683A
MIL-STD-1553 establishes requirements for digital command/response time division multiplexing (TDM) techniques on military vehicles, especially aircraft. The existing MIL-STD-1553 network operates at a bit rate of 1 Mbps and is limited by the protocol to a maximum data payload capacity of approximately 700 kilobits per second. The limited capacity of MIL-STD-1553 buses coupled with emerging data rich applications for avionics platforms plus the expense involved with changing or adding wires to thousands of aircraft in the fleet has driven the need for expanding the data carrying capacity of the existing MIL-STD-1553 infrastructure.
Standard

High Performance 1553 Research and Development

2007-02-21
HISTORICAL
AIR5683
MIL-STD-1553 establishes requirements for digital command/response time division multiplexing (TDM) techniques on military vehicles, especially aircraft. The existing MIL-STD-1553 network operates at a bit rate of 1 Mbps and is limited by the protocol to a maximum data payload capacity of approximately 700 kilobits per second. The limited capacity of MIL-STD-1553 buses coupled with emerging data rich applications for avionics platforms plus the expense involved with changing or adding wires to thousands of aircraft in the fleet has driven the need for expanding the data carrying capacity of the existing MIL-STD-1553 infrastructure.
Standard

High Speed Network for MIL-STD-1760

2012-07-25
HISTORICAL
AS5653A
AS5653 may be applied to Air Vehicles and Stores implementing MIL-STD-1760 Interface Standard for Aircraft/Store Electrical Interconnection System.
Standard

High Speed Network for MIL-STD-1760

2014-01-03
CURRENT
AS5653B
AS5653 may be applied to Air Vehicles and Stores implementing MIL-STD-1760 Interface Standard for Aircraft/Store Electrical Interconnection System.
Standard

Linear Token Passing Multiplex Data Bus User's Handbook

1992-12-30
HISTORICAL
AIR4288
This document is intended to explain, in detail, the rationale behind the features and functions of the AS4074, Linear, Token-passing, Bus (LTPB). The discussions also address the considerations which a system designer should take into account when designing a system using this bus. Other information can be found in these related documents:
Standard

Linear Token Passing Multiplex Data Bus User's Handbook

2012-05-03
CURRENT
AIR4288A
This document is intended to explain, in detail, the rationale behind the features and functions of the AS4074, Linear, Token-passing, Bus (LTPB). The discussions also address the considerations which a system designer should take into account when designing a system using this bus. Other information can be found in these related documents: AIR4271 - Handbook of System Data Communication AS4290 - Validation Test Plan for AS4074
Standard

OPTICAL IMPLEMENTATION RELATING TO THE HIGH SPEED RING BUS (HSRB) STANDARD

1995-01-01
HISTORICAL
AS4075/1
This SAE Aerospace Standard (AS) has been prepared by the Ring Implementation Task Group of the SAE AS-2 Committee. It is intended as a companion document to the SAE AS4075 High Speed Ring Bus Standard. While the Standard is intended to provide as complete a description as possible of an HSRB implementation, certain parameters are system-dependent and evolutionary. This document contains those parameters. The text through Table 1 is intended to provide definitions and descriptions applicable to all applications. Table 2 contains specific parameter values for one or more implementations. This table will change as new systems are implemented or new HSRB speed options are defined.
Standard

Optical Implementation Relating to the High Speed Ring Bus (HSRB) Standard

2012-05-03
CURRENT
AS4075/1A
This SAE Aerospace Standard (AS) has been prepared by the Ring Implementation Task Group of the SAE AS-2 Committee. It is intended as a companion document to the SAE AS4075 High Speed Ring Bus Standard. While the Standard is intended to provide as complete a description as possible of an HSRB implementation, certain parameters are system-dependent and evolutionary. This document contains those parameters. The text through Table 1 is intended to provide definitions and descriptions applicable to all applications. Table 2 contains specific parameter values for one or more implementations. This table will change as new systems are implemented or new HSRB speed options are defined.
Standard

PI-BUS

1993-05-10
HISTORICAL
AS4710
This document is a result of the desire for interoperability of modules on a Pi-Bus. This standard is a stand alone document that used the Very High Speed Integrated Circuit (VHSIC) Phase 2, Interoperability Standard PI-Bus Specification 2.2, as a starting point.
Standard

PI-Bus

2012-05-03
CURRENT
AS4710A
This document is a result of the desire for interoperability of modules on a Pi-Bus. This standard is a stand alone document that used the Very High Speed Integrated Circuit (VHSIC) Phase 2, Interoperability Standard Pi-Bus Specification 2.2, as a starting point.
Standard

Type F-1 Fiber Optic Media Interface Characteristics

2016-10-21
CURRENT
AS4074/1B
This slash sheet specifies the operational parameters and characteristics of a particular implementation of the SAE Linear, Token Passing Bus (LTPB) Interface Unit. This slash sheet defines the following: a The physical media interface: This slash sheet specifies the characteristics of the optical interface to the physical bus media. b The minimum and maximum timing requirements for operation of this implementation of the LTPB. c The data coding used to encode and decode the data for transmission. d The default values to be loaded into the timers of the LTPB interface at power-up prior to intervention by the host processor.
Standard

Type F-1 Fiber Optic Media Interface Characteristics

1993-12-01
HISTORICAL
AS4074/1
This slash sheet specifies the operational parameters and characteristics of a particular implementation of the SAE Linear, Token Passing Bus (LTPB) Interface Unit. This slash sheet defines the following: a The physical media interface: This slash sheet specifies the characteristics of the optical interface to the physical bus media. b The minimum and maximum timing requirements for operation of this implementation of the LTPB. c The data coding used to encode and decode the data for transmission. d The default values to be loaded into the timers of the LTPB interface at power-up prior to intervention by the host processor.
Standard

Type F-1 Fiber Optic Media Interface Characteristics

2004-10-14
HISTORICAL
AS4074/1A
This slash sheet specifies the operational parameters and characteristics of a particular implementation of the SAE Linear, Token Passing Bus (LTPB) Interface Unit. This slash sheet defines the following: a The physical media interface: This slash sheet specifies the characteristics of the optical interface to the physical bus media. b The minimum and maximum timing requirements for operation of this implementation of the LTPB. c The data coding used to encode and decode the data for transmission. d The default values to be loaded into the timers of the LTPB interface at power-up prior to intervention by the host processor.
Standard

Type F-2 Fiber Optic Media Interface Characteristics

2016-10-21
CURRENT
AS4074/2B
This slash sheet specifies the operational parameters and characteristics of a particular implementation of the SAE Linear, Token Passing Bus (LTPB) Interface Unit. This slash sheet defines the following: a The physical media interface: This slash sheet specifies the characteristics of the optical interface to the physical bus media. b The minimum and maximum timing requirements for operation of this implementation of the LTPB. c The data coding used to encode and decode the data for transmission. d The default values to be loaded into the timers of the LTPB interface at power-up prior to intervention by the host processor.
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