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The classical V-cycle methodology for the design of embedded automotive systems is typically implemented by a sequence of steps, from a functional specification down to the implementation at the programming level with the support of an RTOS. The validation of the design is a complex task that consists of analyzing and verifying by testing both functional and non-functional requirements. An important subset of non-functional requirements consists of timing constraints. Implementation must be checked against any violation of the latency and schedulability constraints; otherwise the functionality of the entire system could be severely compromised. Unfortunately, even in state-of-the-art processes, this step is not supported by adequate methods and tools. Subsequently, the process is error-prone and subject to implementation errors, and it is very difficult to generate derivative designs.