Search Results

Automotive HW/SW architectures are becoming increasingly complex to support the deployment of new safety, comfort, and energy-efficiency features. Such architectures include several software tasks (100+), messages (1000+), computational and communication resources (70+ CPUs, 10+ buses), and (smart) sensors and actuators (20+). To cope with the increasing system complexity at lowest development and product costs, highest safety, and fastest time to market, model-based rapid-prototyping development processes are essential. The processes, coupled with optimization steps aimed at reducing the number of software and hardware resources while satisfying the safety requirements, enable reduction of the system complexity and ease downstream testing/validation efforts. This paper describes a novel model-based design exploration and optimization process for the deployment of a set of software tasks on a dual-processor control module implementing a fail-safe strategy.

The sound decomposition of system level timing requirements, including end-to-end deadlines, into local timing requirements and latency budgets is a key automotive design challenge. In this paper, we analyze the technical and organizational influences on the end-to-end deadline decomposition. We will identify and assess typical design options. From this, we provide two key contributions: First, we provide guidelines for the decomposition and the application of design rules. Secondly, we analyze the specific requirements and specialties of different use cases. The findings of this paper enable optimizations and traceability of timing requirements through the entire Electrics/Electronics (E/E) design cycle. This is a prerequisite for reliable, cost-efficient automotive system design.

Vehicle communication networks are challenged by increasing demands for bandwidth, safety, and security. New data is coming into the vehicle from personal devices (e.g. mobile phones), infotainment systems, camera-based driver assistance, and wireless communication with other vehicles and infrastructure. Ethernet (IEEE 802.3) provides high levels of bandwidth and security, making it a potential solution to the challenges of vehicle communication networks. However, in order to be used in control applications, Ethernet must provide known timing performance (e.g. bounded latency and jitter), and in some cases redundancy. This paper explores use of Ethernet for in-vehicle control applications.

Multi-core systems are promising a cost-effective solution for (1) advanced vehicle features requiring dramatically more software and hence an order of magnitude more processing power, (2) redundancy and mixed-IP, mixed-ASIL isolation required for ISO 26262 functional safety, and (3) integration of previously separate ECUs and evolving embedded software business models requiring separation of different software parts. In this context, designing, optimizing and verifying the mapping and scheduling of software functions onto multiple processing cores becomes key. This paper describes several multi-core task design and scheduling design options, including function-to-task mapping, task-to-core allocation (both static and dynamic), and associated scheduling policies such as rate-monotonic, criticality-aware priority assignment, period transformation, hierarchical partition scheduling, and dynamic global scheduling.