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Time Triggered networking technologies such as TTP (Time Triggered Protocol) are beginning to be used in critical aerospace applications such as flight controls. While TTP provides stringent specifications for determinism and fault tolerance, it does not define a physical layer. TTP's “de facto” physical layer, RS-485, includes shortcomings in a number of areas. These include a relatively low minimum transmitter voltage, low receiver threshold, along with a lack of specificity in a number of areas. The latter include bus signal levels, transmitter zero-crossing distortion and receiver zero-crossing tolerance, isolation method, terminal output noise, common mode and noise rejection, and input impedance. MIL-STD-1553, which has been deployed in flight and mission critical military applications for decades, defines a highly proven and robust physical layer. This paper presents MIL-STD-1553's physical layer as a candidate for use with TTP.

System requirements and Interface Control Drawings (ICDs) make a variety of demands for MIL-STD-1553 remote terminals (RTs). Among these requirements are the need to ensure data integrity and sample data consistency, the need to perform bulk (multi-message) data transfers, and the need to offload the operation of the host CPU to the greatest degree possible. This latter requirement is reflected in such specifications as CPU spare bandwidth. The latest 1553 terminals provide a variety of choices for performing the different types of transfers. This paper provides a discussion of the hardware and software techniques for achieving these objectives. Three different schemes for RT subaddress memory management are presented: single message, circular buffer, and double buffered. For receive and transmit messages, these include fully synchronous single message transfers, asynchronous single message transfers, and multi-message transfers.

In addition to supporting the full repertoire of bus controller functions required for the protocol portion of the R.T. Production Test Plan, the latest generation of low cost 1553 protocol testers provides versatile capabilities for remote terminal simulation and real-time monitoring. When used in conjunction with a very low cost “Noise” (Word Error Rate) tester, such a protocol tester is capable of performing the “Bus Switching” test for dual redundancy. This class of noise tester provides all the necessary hardware and firmware required to perform the Word Error Rate Test of the R.T. Validation (SEAFAC) test, including the noise source. Both instruments are fully controllable by means of the IEEE-488 (GPIB) interface, including DMA capability for the protocol tester.