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A variety of methodologies to use embedded multicore controllers efficiently has been discussed in the last years. Several assumptions are usually made in the automotive domain, such as static assignment of tasks to the cores. This paper shows an approach for efficient task allocation depending on different system modes. An engine management system (EMS) is used as application example, and the performance improvement compared to static allocation is assessed. The paper is structured as follows: First the control algorithms for the EMS will be classified according to operating modes. The classified algorithms will be allocated to the cores, depending on the operating mode. We identify mode transition points, allowing a reliable switch without neglecting timing requirements. As a next step, it will be shown that a load distribution by mode-dependent task allocation would be better balanced than a static task allocation.

The increasingly stringent requirements in relation to emission reduction and onboard diagnostics are pushing the Chinese automotive industry toward more innovative solutions and a rapid increase in electronic control performance. To manage the system complexity the architecture will require being well structure on hardware and software level. The paper introduces GEMS-K1 (Gasoline Engine Management System - Kit 1). GEMS-K1 is a platform being compliant with Euro IV emission regulation for gasoline engines. The application software is developed using modeling language, the code is automatically generated from the model. The driver software has a well defined structure including microcontroller abstraction layer and ECU abstraction layer. The hardware is following design rules to be robust, 100% testable and easy to manufacture. The electronic components use the latest innovation in terms of architecture and technologies.

Infineon's latest high-end automotive microcontrollers like TC1796 are complex Systems On Chip (SoC) with two processor cores and up to two internal multi-master buses. The complex interaction between cores, peripherals and environment provides a big challenge for debugging. For mission critical control like engine management the debugging approach must not be intrusive. The provided solution are dedicated Emulation Devices which are able to deal with several 10 Gbit/s of raw internal trace data with nearly no cost adder for mass production and system design. Calibration, which is used later in the development cycle, has different requirements, but is covered by the Emulation Devices as well. The architecture of TC1796ED comprises the unchanged TC1796 silicon layout, extended by a full In-Circuit Emulator (ICE) and calibration overlay memory on the same die. In most cases, the only debug/calibration tool hardware needed is a USB cable.

Infineon proposes a Quasi-Autonomous Gate Driver (QAGD) to manage an electrically actuated component, whether electromechanical, electromagnetic, or electrohydraulic. This paper examines some current control strategies that can be implemented within the QAGD, such as: Synchronous Sampling (SYSA), Hysteresis, Improved Synchronous Sampling-Hysteresis (ISSH), Suboscillation, Suboscillation with Back EMF Feedforward (SBEF) and Synchronous Control in Rotation Coordinates (SCRC). Analysis and simulation of these strategies indicate their advantages and disadvantages, which are then summarized in a comparison chart, from which the best solution for a given application can be determined. The QAGD IC proposed by Infineon adopts this solution by integrating the current controller and the driver unit for the MOSFETs in a single package. The inverter function can therefore be implemented using one QAGD and several MOSFETs, which greatly simplify the system and decrease the costs.

The aim of this paper is to compile the state of the art of engine control and develop scenarios for improvements in a number of applications of engine control where the pace of technology change is at its most marked. The first application is control of downsized engines with enhancement of combustion using direct injection, variable valve actuation and turbo charging. The second application is electrification of the powertrain with its impact on engine control. Various architectures are explored such as micro, mild, full hybrid and range extenders. The third application is exhaust gas after-treatment, with a focus on the trade-off between engine and after-treatment control. The fourth application is implementation of powertrain control systems, hardware, software, methods, and tools. The paper summarizes several examples where the performance depends on the availability of control systems for automotive applications.

Multi-core systems are adopted quickly in the automotive domain, Proof of concepts have been implemented for power train, body and chassis, involving hard real-time constraints. However, depending on the degree of integration, it can be costly, especially in those cases where existing single-core software has to be migrated over. Furthermore, there seems to be a high level of uncertainty, whether a found solution, with regards to partitioning, mapping and orchestration of software is close to an optimum solution. Some integrated solutions demonstrate considerably less performance, for instance due to communication overhead compared to execution on single-core systems. This paper discusses a methodology, as to how to effectively and efficiently investigate the software architecture design space for multi-core software development.

This paper will give an overview of multicore in automotive applications, covering the trends, benefits, challenges, and implementation scenarios. The automotive silicon industry has been building multicore and multiprocessor systems for a long time. The reasons for this choice have been: increased performance, safety redundancy, increased I/O & peripheral, access to multiple architectures (performance type e.g. DSP) and technologies. In the past, multiprocessors have been mainly considered as multi-die, multi-package with simple interconnection such as serial or parallel busses with possible shared memories. The new challenge is to implement a multicore, micro-processor that combines two or more independent processors into a single package, often a single integrated circuit (IC). The multicores allow a computing device to exhibit some form of thread-level parallelism (TLP).