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The concepts of Verification and Validation (V&V) can be oversimplified in a succinct manner by saying that “verification is doing things right” and “validation is doing the right thing”. In the world of the Finite Element Method (FEM) and computational analysis, it is sometimes said “verification means solving the equations right” and “validation means solving the right equations”. In other words, if one intends to give an answer to the equation “2+2=”, then one must run the resulting code to assure that the answer “4” results. However, if the nature of the physics or engineering problem being addressed with this code is multiplicative rather than additive, then even though Verification may succeed (2+2=4 etc), Validation will fail because the equations coded are not those needed to address the real world (multiplicative) problem.