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Vehicle ride comfort and handling demands conflicting design requirements from a vehicle suspension system. As a result, a passive vehicle suspension is incapable of providing the optimum performance for both ride and stability. A test set up is presented in this paper to enable a developer to test any given control algorithm on real-time hardware for an active vehicle suspension, and simulate quarter car performance characteristics. A quarter car model is developed in a host computer and then embedded in a target computer. The parameters of the quarter car are accessible for modification in host computer through TCP/IP connection with target computer. Ride and stability performance characteristics are calculated and also made available during HIL simulation. A controller including a DSP card works with a third computer, where the control system architecture can be edited and control parameters can be changed using a customizable graphical user interface.

Model based design has proven itself as a key enabler to accelerate the development and enhance the quality of embedded software during the last decade. The tools serving the model based design have continuously improved both in terms of software and hardware, and have achieved a maturity level capable to provide seamless transition across different development phases. This approach provides a capability to ensure the satisfaction of key requirements not only at controls development level but also at system level directly addressing the customer requirements. This paper demonstrates a modeling architecture utilizing this capability, allowing the user work on the complete system model that is capable to maintain the same model architecture starting from pure model simulation phase working its way through vehicle testing, contributing to the reduction of the development time and system integration effort while improving the utilization of the model based tools and methods.

This paper presents a uniquely integrated environment where a control system is modeled, simulated and implemented in real time requiring no coding, no compiling nor embedding for multiple test rigs. The novel hardware architecture simultaneously configures itself according to the contents of a visual configuration editor (VCE) that is put together by the user utilizing graphical representations of basic building blocks called primitives. Similar to an analog computer, as the user builds the VCE model, the “code is simultaneously compiled and embedded” into the target DSP processor/s as easy as dragging and dropping primitives from various libraries into the VCE and connecting them. Similarly DSP processors within the hardware network are visually available to the user to be dropped into the VCE creating a distributed multi-processor control environment. The execution of multiple DSPs take place simultaneously reaching 25.6 kHz loop rates and 200 kz sampling rates.