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This document describes a process for use by ADHP integrators of EEE parts and sub-assemblies (items) that have been targeted for other applications. This document does not describe specific tests to be conducted, sample sizes to be used, nor results to be obtained; instead, it describes a process to define and accomplish application-specific qualification; that provides confidence to both the ADHP integrators, and the integrators’ customers, that the item will performs its function(s) reliably in the ADHP application.

This document applies to the development of Plans for integrating and managing COTS assemblies in electronic equipment and Systems for the commercial, military, and space markets; as well as other ADHP markets that wish to use this document. For purposes of this document, COTS assemblies are viewed as electronic assemblies such as printed wiring assemblies, relays, disk drives, LCD matrices, VME circuit cards, servers, printers, laptop computers, etc. There are many ways to categorize COTS assemblies1, including the following spectrum: At one end of the spectrum are COTS assemblies whose design, internal parts2, materials, configuration control, traceability, reliability, and qualification methods are at least partially controlled, or influenced, by ADHP customers (either individually or collectively). An example at this end of the spectrum is a VME circuit card assembly.

This document is intended for use by designers, reliability engineers, and others associated with the design, production, and support of electronic sub-assemblies, assemblies, and equipment used in AADHP applications to conduct lifetime assessments of microcircuits with the potential for early wearout; and to implement mitigations when required; and by the users of the AADHP equipment to assess those designs and mitigations. This document focuses on the LLM wearout assessment process. It acknowledges that the AADHP system design process also includes related risk mitigation and management; however, this document includes only high-level reference and discussion of those topics, in order to show their relationship to the LLM assessment process.

This document describes a process for use by ADHP integrators of EEE parts and sub-assemblies (items) that have been targeted for other applications2. This document does not describe specific tests to be conducted, sample sizes to be used, nor results to be obtained; instead, it describes a process to define and accomplish application-specific qualification; that provides confidence to both the ADHP integrators, and the integrators’ customers, that the item will performs its function(s) reliably in the ADHP application.

This document is intended for use by designers, reliability engineers, and others associated with the design, production, and support of electronic sub-assemblies, assemblies, and equipment used in ADHP applications to conduct lifetime assessments of microcircuits with the potential for early wearout; and to implement mitigations when required; and by the users of the ADHP equipment to assess those designs and mitigations. This document focuses on the LLM wearout assessment process. It acknowledges that the ADHP system design process also includes related risk mitigation and management; however, this document includes only high-level reference and discussion of those topics, in order to show their relationship to the LLM assessment process.

This document applies to the development of Plans for integrating and managing COTS assemblies in electronic equipment and Systems for the commercial, military, and space markets; as well as other ADHP markets that wish to use this document. For purposes of this document, COTS assemblies are viewed as small electronic assemblies such as printed wiring assemblies, relays, disk drives, LCD matrices, VME circuit cards, servers, printers, laptop computers, etc. There are many ways to categorize COTS assemblies1, including the following spectrum: At one end of the spectrum are COTS assemblies whose design, internal parts2, materials, configuration control, and qualification methods are at least partially controlled, or influenced, by aerospace customers (either individually or collectively). An example at this end of the spectrum is a VME circuit card assembly.

This document applies to the development of plans for the integration and management of COTS assemblies in electronic systems used in the commercial, military and space markets. COTS assemblies include items such as VPX circuit cards/modules (single board computers, etc.), servers, printers, laptop computers, printed wiring assemblies, disk drives, etc. This publication is not intended to preclude or discourage other approaches that similarly represent good engineering practice, or that may be acceptable to, or have been accepted by, appropriate bodies. Parties who wish to bring other approaches to the attention of the formulating committee to be considered for inclusion in future drafts of this publication are encouraged to do so. It is the intention of the formulating committee to revise and update this publication from time to time as may be occasioned by changes in technology, industry practice, or government regulations, or for other appropriate reasons.