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Infineon's latest high-end automotive microcontrollers like TC1796 are complex Systems On Chip (SoC) with two processor cores and up to two internal multi-master buses. The complex interaction between cores, peripherals and environment provides a big challenge for debugging. For mission critical control like engine management the debugging approach must not be intrusive. The provided solution are dedicated Emulation Devices which are able to deal with several 10 Gbit/s of raw internal trace data with nearly no cost adder for mass production and system design. Calibration, which is used later in the development cycle, has different requirements, but is covered by the Emulation Devices as well. The architecture of TC1796ED comprises the unchanged TC1796 silicon layout, extended by a full In-Circuit Emulator (ICE) and calibration overlay memory on the same die. In most cases, the only debug/calibration tool hardware needed is a USB cable.

In terms of modern technical systems, the automotive sector is characterized by escalating complexity and functionality requirements. The development of embedded control systems has to meet highest demands regarding process-, time- and cost-optimization. Hence, the efficiency of software development becomes a crucial competitive advantage. Systems design engineers need effective tools and methods to achieve exemplary speed and productivity within the development phase. To obtain such tools and methods, semiconductor manufacturers and tool manufacturers must work closely together. Within the joint efforts of ETAS and Infineon, the software tool suite ASCET-SD was enhanced to generate efficient C code for Infineon's TriCore architecture mapped on ETAS's real-time operating system ERCOSEK. The processor interface to application & calibration tools was realized using the ETK probe based on a JTAG/Nexus link at very high bandwidth.

In defining innovative and cost-effective chip sets for future automotive applications, system architects need high-level tools that allow them to rapidly determine the best silicon partitioning for a given application in terms of system performance as well as cost. The tool needs to be flexible, modular, and swift such that the system designer can perform abstract simulation iterations quickly for various functional partitioning scenarios, without requiring excessive computer resources. The tool must also be portable and adaptable to provide a simulation environment suitable to systems- or car-manufacturers for in-depth applications simulation and architecture assessment. The semiconductor component definition process using such a “mission-level” design tool for the automotive application electronic valve will be demonstrated. Methods for the analysis of electronic valve control system architectures using mission-level simulation will be developed.

End of Line tests are brief set of tests intended to evaluate ECU's in order to ensure correct functioning of its intended functionality. As these tests are executed on the production line, available time to perform these tests is limited. On one hand, faster production demands require these tests and its framework to be designed in a time optimized manner. On the other hand, increase in ECU functionality translates to an increase in test's functional coverage, requiring more time. Therefore the time taken to execute the tests reaches a critical point in overall ECU production. Availability of multicore microcontrollers with increase in clock speed can increase the performance of end of line tests, but design challenges e.g. synchronization do not guarantee a linear performance increase. Therefore, design of test execution framework is absolutely critical to increase performance of test execution.