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Due to the increase in demand for comfort and safety features in today's automobiles, the internal vehicle communication networks necessary to accommodate these features are very complex. These networks represent a heterogeneous architecture consisting of several ECUs exchanging information via bus systems such as CAN, LIN, MOST, or FlexRay buses. Development and verification of internal vehicle networks include multiple design layers. These layers are the logical layer represented by the software application, the associated data link layer, and the physical connection layer containing bus interfaces, wires, and termination. Verification of these systems in the early stages of the design process (before a physical network is available for testing) has become a critical need. As a result, the need to simulate these designs at all their levels of complexity has become critically important.

New technologies such as multi-core and Ethernet provide vastly improved computing and communications capabilities. This sets the foundation for the implementation of new digital megatrends in almost all areas: driver assistance, vehicle dynamics, electrification, safety, connectivity, autonomous driving. The new challenge: We must share these computing and communication capacities among all vehicle functions and their software. For this step, we need a good resource planning to minimize the probability of late resource bottlenecks (e.g. overload, lack of real-time capability, quality loss). In this article, we summarize the status quo in the field of resource management and provide an outlook on the challenges ahead.

With the increasing complexity of electronic vehicle systems, one particular “gap” between function development and ECU integration becomes more and more apparent, and critical; albeit not new. The core of the problem is: as more functions are integrated and share the same E/E resources, they increasingly mutually influence and disturb each other in terms of memory, peripherals, and also timing and performance. This has two consequences: The amount of timing-related errors increases (because of the disturbance) and it becomes more difficult to find root causes of timing errors (because of the mutual influences). This calls for more systematic methods to deal with timing requirements in general and their transformation from function timing requirements to software architecture timing requirements in particular.