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GTL (Gas-To-Liquid) fuel is well known to improve tailpipe emissions when fuelling a conventional diesel vehicle, that is, one optimized to conventional fuel. This investigation assesses the additional potential for GTL fuel in a GTL-dedicated vehicle. This potential for GTL fuel was quantified in an EU 4 6-cylinder serial production engine. In the first stage, a comparison of engine performance was made of GTL fuel against conventional diesel, using identical engine calibrations. Next, adaptations enabled the full potential of GTL fuel within a dedicated calibration to be assessed. For this stage, two optimization goals were investigated: - Minimization of NOx emissions and - Minimization of fuel consumption. For each optimization the boundary condition was that emissions should be within the EU5 level. An additional constraint on the latter strategy required noise levels to remain within the baseline reference.

Fully variable valve trains provide comprehensive means of adjustment in terms of variable valve timing and valve lift. The efficiency of the engine is improved in the operating range and in return, an increasing complexness of the mechanical design and control engineering must be handled. For optimization and design of these kinds of complex systems, detailed simulation models covering different physical domains, i.e. mechanics, hydraulics, electrodynamics and control are needed. Topic of this work is the variable valve train named Audi valvelift system (AVS) e.g. used in the Audi 2.8l V6 FSI engine. The idea of AVS is to use different cam lobes at different operating points. Each intake valve can be actuated by a large and a small cam. For full load, the two inlet valves are opened by the large cam profile - ideal for high charge volumes and flow speeds in the combustion chamber. Under partial load, the small cam profiles are used.

A variety of methodologies to use embedded multicore controllers efficiently has been discussed in the last years. Several assumptions are usually made in the automotive domain, such as static assignment of tasks to the cores. This paper shows an approach for efficient task allocation depending on different system modes. An engine management system (EMS) is used as application example, and the performance improvement compared to static allocation is assessed. The paper is structured as follows: First the control algorithms for the EMS will be classified according to operating modes. The classified algorithms will be allocated to the cores, depending on the operating mode. We identify mode transition points, allowing a reliable switch without neglecting timing requirements. As a next step, it will be shown that a load distribution by mode-dependent task allocation would be better balanced than a static task allocation.

The newly released Distributed System Interface 3 (DSI3) Bus Standard specification defines three modulation levels form which 16 valid symbols are coded. This complex structure is best decoded with symbol pattern recognition. This paper proposes a simplification of the correlation score calculation that sharply reduces the required number of operations. Additionally, the paper describes how the pattern recognition is achieved using correlation scores and a decoding algorithm. The performance of this method is demonstrated by mean of simulations with different load models between the master and the sensors and varying noise injection on the channel. We prove than the pattern recognition can decode symbols without any error for up to 24dBm.

This paper discusses the RDC method utilizing delta-sigma analog-to-digital converter hardware module (DSADC) integrated in the Infineon's microcontroller family. With its higher resolution capability when compared to the regularly used ADC with successive-approximation (SAR), DSADC seems to have more potential. On the other hand, DSADC's inherent properties, such as asynchronous sampling rate and group delay, which when not handled properly, would have negative effects to the rotor positioning system. The solution to overcome those side-effects involves utilization of other internal microcontroller's resources such as timers and capture units, as well as additional software processing run inside CPU. The rotor positioning system is first modeled and simulated in high-level simulation language environment (Matlab and Simulink) in order to predict the transient- and steady state behaviors. The group delay itself is obtained by simulating the model of DSADC module implementation.

In-vehicle communication faces increasing bandwidth demands, which can no longer be met by today's MOST150, FlexRay or CAN networks. In recent years, Fast Ethernet has gained a lot of momentum in the automotive world, because it promises to bridge the bandwidth gap. A first step in this direction is the introduction of Ethernet as an On Board Diagnostic (OBD) interface for production vehicles. The next potential use cases include the use of Ethernet in Driver Assistance Systems and in the infotainment domain. However, for many of these use cases, the Fast Ethernet solution is too slow to move the huge amount of data between the Domain Controllers, ADAS Systems, Safety Computer and Chassis Controller in an adequate way. The result is the urgent need for a network technology beyond the Fast Ethernet solution. The question is: which innovation will provide enough bandwidth for domain controllers, fast flashing routines, video data, MOST-replacement and internal ECU buses?

The open jet wind tunnel is a widespread test section configuration for developing full scale passenger cars in the automotive industry. However, using a realizable nozzle cross section for cost effective aerodynamic development is always connected to the presence of wind tunnel effects. Wind tunnel wall interferences which are not present under open road conditions, can affect the measurement of aerodynamic forces. Thus, wind tunnel corrections may be required. This work contains the results of a CFD (Computational Fluid Dynamics) approach using unsteady Delayed Detached Eddy Simulations (DDES) to evaluate wind tunnel interferences for open jet test sections. The Full Scale DrivAer reference geometry of the Technical University of Munich (TUM) using different rear end shapes has been selected for these investigations.

With the introduction of the ISO26262 automotive safety standard there is a burden of proof to show that the processing elements in embedded microcontroller hardware are capable of supporting a certain diagnostic coverage level, depending on the required Automotive Safety Integrity Level (ASIL). The current mechanisms used to provide actual metrics of the Built-in Self Tests (BIST) and Lock Step comparators use Register Transfer Level (RTL) simulations of the internal processing elements which force faults into individual nodes of the design and collect diagnostic coverage results. Although this mechanism is robust, it can only be performed by semiconductor suppliers and is costly. This paper describes a new solution whereby the microcontroller is synthesized into a large Field Programmable Gate Array (FPGA) with a test controller on the outside.

This study deals with the experimental investigation of the mechanical properties of a lithium-ion pouch cell and its modelling in an explicit finite element simulation code. One can distinguish between ‘macroscopic’ and ‘microscopic’ modelling approaches. In the ‘macroscopic’ approach, one material model approximates the behaviour of multiple inner cell layers. In the ‘microscopic’ approach, which is used in the present study, all layers and their interactions are modelled separately. The cell under study is a pouch-type lithium-ion cell with a liquid electrolyte. With its cell chemistry, design, size and capacity it is usable for automotive applications and can be assembled into traction batteries. One cell sample was fully discharged and disassembled, and its components (anode, cathode, separator and pouch) were examined and measured by electron microscopy. Components were also tensile tested.

More than ever, microcontroller performance in cars has a direct impact on the driving experience, on compliance with improved safety, ever-stricter emissions regulations, and on fuel economy. The simple microcontrollers formerly used in automobiles are now being replaced by powerful number-crunchers with incredible levels of peripheral integration. As a result, performance can no longer be measured in MIPS (Millions of Instructions Per Second). A microcontroller's effectiveness is based on coherent partitioning between analog and digital, hardware and software, tools and methodology. To make an informed choice among the available devices, the designer needs benchmarks that are specific to automotive applications, and which provide a realistic representation of how the device will perform in the automotive environment.

More than ever, microcontroller performance in cars has a direct impact on the driving experience, on compliance with improved safety, ever-stricter emissions regulations, and on fuel economy. The simple microcontrollers formerly used in automobiles are now being replaced by powerful number-crunchers whose performance can no longer be measured in MIPS. Instead, their effectiveness is based on a coherent partitioning between analog and digital, hardware and software, tools and methodology. To make an informed choice among the available devices, what the designer needs are benchmarks that are specific to automotive applications, and which provide a realistic representation of how the device will perform in the automotive environment. This presentation will explore the role of new benchmarks in the development of complex automotive applications.

Electronic Control Units of safety critical systems require constant monitoring of the hardware to be able to bring the system to a safe state if any hardware defects or malfunctions are detected. This monitoring includes memory checking, peripheral checking as well as checking the main processor core. However, checking the processor core is difficult because it cannot be guaranteed that the error will be properly detected if the monitor function is running on a processing system which is malfunctioning. To circumvent this issue, several previously presented monitoring concepts (e.g. SAE#2006-01-0840) employ a second external microprocessor to communicate with the main processor to check its integrity. The addition of a second microcontroller and the associated support circuitry that is required adds to the overall costs of the ECU, increases the size and creates significant system complexity.

Electronic Control Units of safety critical systems require constant monitoring of the hardware to be able to bring the system to a safe state if any hardware defects or malfunctions are detected. This monitoring includes memory checking, peripheral checking as well as checking the main processor core. However, checking the processor core is difficult because it cannot be guaranteed that the error will be properly detected if the monitor function is running on a processing system which is malfunctioning. To circumvent this issue, several previously presented monitoring concepts (e.g. SAE#2006-01-0840) employ a second external microprocessor to communicate with the main processor to check its integrity. This paper will present a concept which maps the functions of the external monitoring unit into an internal second processing core which are frequently available on modern, 32bit, monolithic, dual-core microcontrollers.

More and more high-level algorithms are emerging to improve the existing systems in a car. Often these algorithms only need a platform with a bus connection and some resources such as CPU time and memory space. These functions can easily be integrated into existing systems that have free resources. This paper describes some encapsulation techniques and mechanisms that can be used in the automotive domain. The discussion also takes into account the additional resources consumed on the microcontroller to meet these requirements and by the software to implement the encapsulation mechanisms. Overviews of some general concepts of software-architectures that provide encapsulation are also shown.

The increasingly stringent requirements in relation to emission reduction and onboard diagnostics are pushing the Chinese automotive industry toward more innovative solutions and a rapid increase in electronic control performance. To manage the system complexity the architecture will require being well structure on hardware and software level. The paper introduces GEMS-K1 (Gasoline Engine Management System - Kit 1). GEMS-K1 is a platform being compliant with Euro IV emission regulation for gasoline engines. The application software is developed using modeling language, the code is automatically generated from the model. The driver software has a well defined structure including microcontroller abstraction layer and ECU abstraction layer. The hardware is following design rules to be robust, 100% testable and easy to manufacture. The electronic components use the latest innovation in terms of architecture and technologies.

This paper proposes end-to-end protection mechanisms to be added to a generic FlexRay network in order to achieve fault detection and integrity levels sufficient for a SIL3 fail safe communication system. The mechanisms are derived from the random hardware failure modes to be considered for communication controllers according to IEC 61508. Mechanisms provided by the FlexRay protocol are pointed out. Additional features necessary to fulfil the requirements are discussed. It is shown how to calculate the failure rate probabilities of the CRC used as a safety code with respect to EN 50159.

With the ever increasing amount of available software processing resources in a vehicle, more and more high-level algorithms are emerging to improve the existing systems in a car. Often these algorithms only need a platform with a bus connection and some resources such as processing power and memory space. These functions are predestined to be integrated into existing systems that have free resources. This paper will examine the role of time protection in these multi-algorithm systems and describe what timing protection means and why it is required. The processing time will be partitioned to the different processing levels like interrupts, services and tasks. The problems of timing protection will be illustrated as well as its limitations. The conflict between real-time requirements and timing protection will be shown. Finally Autosar will be examined with focus on timing protection and applicability in actual development projects.

This paper considers the verification of non-standard CAN network topologies of the physical layer at high speed transmission rate (500.0Kbps and 1.0Mbps). These network topologies including single star, multiple stars, and hybrid topologies (multiple stars in combination with linear bus or with ring topology) are simulated by using behavior modeling language (VHDL-AMS) in comparison to measurement. Throughout the verification process, CAN transceiver behavioral model together with other CAN physical layer simulation components have been proved to be very accurate. The modeling of measurement environment of the CAN network is discussed, showing how to get the measurement and simulation results well matched. This demonstrates that the simulation solution is reliable, which is highly desired and very important for the verification requirement in CAN physical layer design.

The verification of an in-vehicle network often requires to look at more than one level of abstraction at a time. At the moment, this is not addressed by existing methods, which are dedicated either to physical or application layer, but not both. This paper fills this gap by introducing a methodology to insert the protocol related software execution as well as the motor behavior into the physical layer mixed-signal (i.e. analog/digital) simulation. Electronics and mechanics are covered by the hardware description language VHDL-AMS, while the software is given in C.

Infineon's latest high-end automotive microcontrollers like TC1796 are complex Systems On Chip (SoC) with two processor cores and up to two internal multi-master buses. The complex interaction between cores, peripherals and environment provides a big challenge for debugging. For mission critical control like engine management the debugging approach must not be intrusive. The provided solution are dedicated Emulation Devices which are able to deal with several 10 Gbit/s of raw internal trace data with nearly no cost adder for mass production and system design. Calibration, which is used later in the development cycle, has different requirements, but is covered by the Emulation Devices as well. The architecture of TC1796ED comprises the unchanged TC1796 silicon layout, extended by a full In-Circuit Emulator (ICE) and calibration overlay memory on the same die. In most cases, the only debug/calibration tool hardware needed is a USB cable.