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Multi core platforms offer high performance at low power and have been deemed as future of size, weight and power constrained applications like avionics safety critical applications. Multi core platforms are widely used in non-real time systems where the average case performance is desired like in consumer electronics, telecom domains. Despite these advantages, multi core platforms (hardware and software) pose significant certification challenges for safety critical applications and hence there has been limited usage in avionics and other safety critical applications. Many multicore platform solutions which can be certified to DO-254 & DO 178B Level A are commercially available. There is a need to evaluate these platforms w.r.t certification requirements before deploying them in the safety critical systems thereby reducing the program risks. This paper discusses the advantages of multi core platforms in terms of performance, power consumption and weight/size.

Modern aircraft systems employ numerous processors to achieve system functionality. In particular, engine controls and power distribution subsystems rely heavily on software to provide safety-critical functionality, and are expected to move toward multicore architectures. The computing hardware-layer of avionic systems must be able to execute many concurrent workloads under tight deterministic execution guarantees to meet the safety standards. Single-chip multicores are attractive for safety-critical embedded systems due to their lightweight form factor. However, multicores aggressively share hardware resources, leading to interference that in turn creates non-deterministic execution for multiple concurrent workloads. We propose an approach to remove on-chip interference via a set of methods to spatio-temporally partition shared multicore resources.