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The development of highly automated driving functions (AD) recently rises the demand for so called Fail-Operational systems for native driving functions like steering and braking of vehicles. Fail-Operational systems shall guarantee the availability of driving functions even in presence of failures. This can also mean a degradation of system performance or limiting a system’s remaining operating period. In either case, the goal is independency from a human driver as a permanently situation-aware safety fallback solution to provide a certain level of autonomy. In parallel, the connectivity of modern vehicles is increasing rapidly and especially in vehicles with highly automated functions, there is a high demand for connected functions, Infotainment (web conference, Internet, Shopping) and Entertainment (Streaming, Gaming) to entertain the passengers, who should no longer occupied with driving tasks.

Software complexity of vehicles is constantly growing especially with additional autonomous driving features being introduced. This increases the risk for bugs in the system, when the car is delivered. According to a car manufacturer, more than 90% of availability problems corresponding to Electronic Control Unit (ECU) functionality are either caused by software bugs or they can be resolved by applying software updates to overcome hardware issues. The main concern are sporadic errors which are not caught during the development phase since their trigger condition is too unlikely to occur or is not covered by the tests. For such systems, there is a need of safe and secure infield diagnosis. In this paper we present a tool software architecture with remote access, which facilitates standard read/write access, an efficient channel interface for communication and file I/O, and continuous trace.

Recently, vehicle networks have increased complexity due to the demand for autonomous driving or connected devices. This increasing complexity requires high bandwidth. As a result, vehicle manufacturers have begun using Ethernet-based communication for high-speed links. In order to deal with the heterogeneity of such networks where legacy automotive buses have to coexist with high-speed Ethernet links vehicle manufacturers introduced a vehicle gateway system. The system uses Ethernet as a backbone between domain controllers and CAN buses for communication between internal controllers. As a central point in the vehicle, the gateway is constantly exchanging vehicle data in a heterogeneous communication environment between the existing CAN and Ethernet networks. In an in-vehicle network context where the communications are strictly time-constrained, it is necessary to measure the delay for such routing task.

Autonomous driving systems and connected mobility are the next big developments for the car manufacturers and their suppliers during the next decade. To achieve the high computing power needs and fulfill new upcoming requirements due to functional safety and security, heterogeneous processor architectures with a mixture of different core architectures and hardware accelerators are necessary. To tackle this new type of hardware complexity and nevertheless stay within monetary constraints, high performance computers, inspired by state of the art data center hardware, could be adapted in order to fulfill automotive quality requirements. The European Processor Initiative (EPI) research project tries to come along with that challenge for next generation semiconductors. To be as close as possible to series development needs for the next upcoming car generations, we present a hybrid semiconductor system-on-chip architecture for automotive.

Advanced safety features and new services in connected cars depend on the security of the underlying vehicle functions. Due to the interconnection with the outside world and as a result of being an embedded system a modern vehicle is exposed to both, malicious activities as faced by traditional IT world systems as well as physical attacks. This introduces the need for utilizing hardware-assisted security measures to prevent both kinds of attacks. In this paper we present a survey of the different classes of hardware security devices and depict their different functional range and application. We demonstrate the feasibility of our approach by conducting a case study on an exemplary implementation of a function-on-demand use case. In particular, our example outlines how to apply the different hardware security approaches in practice to address real-world security topics. We conclude with an assessment of today’s hardware security devices.

Driven by the growing internet and remote connectivity of automobiles, combined with the emerging trend to automated driving, the importance of security for automotive systems is massively increasing. Although cyber security is a common part of daily routines in the traditional IT domain, necessary security mechanisms are not yet widely applied in the vehicles. At first glance, this may not appear to be a problem as there are lots of solutions from other domains, which potentially could be re-used. But substantial differences compared to an automotive environment have to be taken into account, drastically reducing the possibilities for simple reuse. Our contribution is to address automotive electronics engineers who are confronted with security requirements. Therefore, it will firstly provide some basic knowledge about IT security and subsequently present a selection of automotive specific security use cases.

The constant motivation for lower fuel consumption and emission levels has always been in the minds of most auto makers. Therefore, it is important to have precise control of the fuel being delivered into the engine. Gasoline Port fuel injection has been a matured system for many years and cars sold in emerging markets still favor such system due to its less system complexity and cost. This paper will explain injection control strategy of today during development, and especially the injector dead-time compensation strategy in detail and how further improvements could still be made. The injector current profile behavior will be discussed, and with the use of minimum hardware electronics, this paper will show the way for a new compensation strategy to be adopted.

The modern day power MOSFET is constructed using the latest technology in order to minimize the drain source resistance. The latest MOSFET technologies are capable of achieving the same drain to source resistance with a smaller MOSFET die than previous generations which will directly lead to increased thermal resistance and limited energy handling capability. This paper will discuss the Safe Operating Area of power MOSFETs and how to assess new MOSFET technology.

This paper presents a reliability study of a directly cooled IGBT module after a test drive of 85,000 Km in a fuel cell electric vehicle, as well as of an indirectly cooled IGBT module after a test drive of 200,000km in a hybrid car on public roads. At the end of the test drive, the inverter units were disassembled and analyzed with regard to the lifetime consumption. First, electrical measurements were carried out and the results were compared with the ones obtained directly after module production (End of Line test). After that, ultrasonic microscopy was performed in order to investigate any delamination in the solder layers. As a third step, an optical inspection was performed to monitor damages in the housing, formation of cracks or degradation of wire bonds. The results show none of the depicted failure modes could be found on the tested power modules after the field test. Obviously, no significant life time consumption could be observed.

The newly released Distributed System Interface 3 (DSI3) Bus Standard specification defines three modulation levels form which 16 valid symbols are coded. This complex structure is best decoded with symbol pattern recognition. This paper proposes a simplification of the correlation score calculation that sharply reduces the required number of operations. Additionally, the paper describes how the pattern recognition is achieved using correlation scores and a decoding algorithm. The performance of this method is demonstrated by mean of simulations with different load models between the master and the sensors and varying noise injection on the channel. We prove than the pattern recognition can decode symbols without any error for up to 24dBm.

Integration scenarios for ECU software become more complicated, as more constraints with regards to timing, safety and security need to be considered. Multi-core microcontrollers offer even more hardware potential for integration scenarios. To tackle the complexity, more and more model based approaches are used. Understanding the interaction between the different software components, not only from a functional but also from a timing view, is a key success factor for high integration scenarios. In particular for multi-core systems, an amazing amount of timing data can be generated. Usually a multi-core system handles more software functionality than a single-core system. Furthermore, there may be timing interference on the multicore systems, due to the shared usage of buses, memory banks or other hardware resources.

In modern vehicles, the number of small electrical drive systems is still increasing continuously for blowers, fans and pumps as well as for window lifts, sunroofs and doors. Requirements and operating conditions for such systems varies, hence there are many different solutions available for controlling such motors. In most applications, simple, low-cost DC motors are used. For higher requirements regarding operating time and in stop-start capable systems, the focus turns to highly efficient and durable brushless DC motors with electronic commutation. This paper compares various electronic control concepts from a semiconductor vendor point of view. These concepts include discrete control using relays or MOSFETs. Furthermore integrated motor drivers are discussed, including system-on-chip solutions for specific applications, e.g. specific ICs for window lift motors with LIN interface.

The electrification of the powertrain is still one of the main challenges and innovation drivers for modern cars. With the introduction of the Toyota Prius, launched in Japan in 1997 the first commercially available hybrid car in mass production, the development continued towards the BMW i3 launched in July 2013. One main component for all kind of hybrid cars is still the power semiconductor, which is used for DC/DC converters and for the inverter to drive the electric motor for the traction control. What makes the selection of the right power semiconductor complex, is the variety of different voltage levels within the car (from standard 12V board net, the new 48V board net all the way up to 400V and above) plus different requirements in terms of switching and conduction performance, or accordingly power losses. The selection of device by application and voltage will be discussed in this paper.

This paper considers the verification of non-standard CAN network topologies of the physical layer at high speed transmission rate (500.0Kbps and 1.0Mbps). These network topologies including single star, multiple stars, and hybrid topologies (multiple stars in combination with linear bus or with ring topology) are simulated by using behavior modeling language (VHDL-AMS) in comparison to measurement. Throughout the verification process, CAN transceiver behavioral model together with other CAN physical layer simulation components have been proved to be very accurate. The modeling of measurement environment of the CAN network is discussed, showing how to get the measurement and simulation results well matched. This demonstrates that the simulation solution is reliable, which is highly desired and very important for the verification requirement in CAN physical layer design.

More than ever, microcontroller performance in cars has a direct impact on the driving experience, on compliance with improved safety, ever-stricter emissions regulations, and on fuel economy. The simple microcontrollers formerly used in automobiles are now being replaced by powerful number-crunchers with incredible levels of peripheral integration. As a result, performance can no longer be measured in MIPS (Millions of Instructions Per Second). A microcontroller's effectiveness is based on coherent partitioning between analog and digital, hardware and software, tools and methodology. To make an informed choice among the available devices, the designer needs benchmarks that are specific to automotive applications, and which provide a realistic representation of how the device will perform in the automotive environment.

This paper will give an overview of multicore in automotive applications, covering the trends, benefits, challenges, and implementation scenarios. The automotive silicon industry has been building multicore and multiprocessor systems for a long time. The reasons for this choice have been: increased performance, safety redundancy, increased I/O & peripheral, access to multiple architectures (performance type e.g. DSP) and technologies. In the past, multiprocessors have been mainly considered as multi-die, multi-package with simple interconnection such as serial or parallel busses with possible shared memories. The new challenge is to implement a multicore, micro-processor that combines two or more independent processors into a single package, often a single integrated circuit (IC). The multicores allow a computing device to exhibit some form of thread-level parallelism (TLP).

Today the majority of power electronics is developed based on the requirements set by the main fields of application e.g. power generation, power supply, industrial drive and traction. With introduction to automotive applications new requirements have to be taken into account. This paper discusses how interconnection technologies for power semiconductors can be improved to meet the demand for higher temperature capability in HEV applications.

More than ever, microcontroller performance in cars has a direct impact on the driving experience, on compliance with improved safety, ever-stricter emissions regulations, and on fuel economy. The simple microcontrollers formerly used in automobiles are now being replaced by powerful number-crunchers whose performance can no longer be measured in MIPS. Instead, their effectiveness is based on a coherent partitioning between analog and digital, hardware and software, tools and methodology. To make an informed choice among the available devices, what the designer needs are benchmarks that are specific to automotive applications, and which provide a realistic representation of how the device will perform in the automotive environment. This presentation will explore the role of new benchmarks in the development of complex automotive applications.

In the case of a side impact the decision to deploy an airbag has to be taken much faster as it would be required for a front impact. Furthermore, there is a significant spread of the measurable acceleration depending on which pillars of the cars side are hit. Measuring the pressure inside the door as a direct result of an impact, the deformation of the door becomes observable. Based on pressure measurements side impacts can be detected much faster and more reliable. Therefore side airbag pressure sensors are established as add-on or replacement for side airbag acceleration sensors. This paper will present a Side Airbag Chip Set comprising of a side airbag pressure sensor and a satellite receiver. The system architecture and the partitioning between a single chip solution for the side airbag pressure sensor module plus the compatible satellite receiver will be described.

For the past approximately 20 years, the Serial Peripheral Interface (SPI) has been the established standard for serial communication between a host or central microprocessor and peripheral devices. This standard has been used extensively in control modules covering the entire spectrum of automotive applications, as well as non-automotive applications. As the complexity of engine control modules grows, with the number of vehicle actuators being controlled and monitored increasing, the number of loads the central microprocessor has to manage is growing accordingly. These loads are typically controlled using discrete and pulse-width modulated (PWM) outputs from the microcontroller when real-time operation is essential or via SPI when real-time response is not critical. The increase of already high pin-count on microcontrollers, the associated routing effort and demand for connected power stages is a concern of cost and reliability for future ECU designs.