Search Results

To cope with the increasing number of advanced features (e.g., smart-phone integration and side-blind zone alert.) being deployed in vehicles, automotive manufacturers are designing flexible hardware architectures which can accommodate increasing feature content with as fewer as possible hardware changes so as to keep future costs down. In this paper, we propose a formal and quantitative definition of flexibility, a related methodology and a tool flow aimed at maximizing the flexibility of an automotive hardware architecture with respect to the features that are of greater importance to the designer. We define flexibility as the ability of an architecture to accommodate future changes in features with no changes in hardware (no addition/replacement of processors, buses, or memories). We utilize an optimization framework based on mixed integer linear programming (MILP) which computes the flexibility of the architecture while guaranteeing performance and safety requirements.

Since the beamforming concept was first introduced to acoustic engineers approximately 10 years ago, the acoustic phased array has become one of the most popular techniques used to identify noise sources. Generally speaking, the spatial resolution of the phased array is proportional to the number of microphones and the array size. With more microphones or a larger array, better spatial resolution is achieved. However, to achieve better spatial resolution for a given microphone array structure, the so-called CLEAN method was recently introduced. By applying the traditional non-parametric estimation method, such as delay-and-sum, the CLEAN algorithm first computes the largest noise and removes it from the raw data samples. Then, the program estimates a new peak noise, based on the “cleaned” data samples. The process is repeated until the remaining data samples become random noise. The CLEAN method works well if the noise sources are far apart.

Modular instrumentation is being widely used in noise and vibration measurement systems that demand higher channel counts and the wider dynamic range that 24-bit delta-sigma ADCs make available at lower costs. This is an overview how flexible modular instrumentation employing the latest software technology can be used in making high precision noise and vibration measurements where higher sampling rates, higher channel counts, increased dynamic range, and distributed architectures were needed in smaller packages. An example where this is being used is in acoustic beam forming in aircraft pass by noise tests to measure and distinguish engine and airframe noise sources.

LIN is a low-cost, low-speed vehicle communication sub-bus becoming increasingly pervasive in automotive subsystems. It is a simple, UART-based master-slave protocol designed as a low-speed supplement to a CAN or FlexRay bus. Its primary application is cabin comfort and human interface hardware such as dashboard controls, power seat harnesses, and power door/window systems. As automotive network designers attempt to reduce wiring complexity and lower system cost, modular, inexpensive sub-buses like LIN become an attractive option. This paper presents an overview of the LIN standard and its applications, and then proposes an architecture for rapid development of LIN networks via hardware simulations of LIN nodes. Using inexpensive, off-the-shelf hardware, LIN sensor and actuator applications can be tested in-place without microcode development, speeding overall network development time.

Companies typically invest significant time and money in choosing the proper test equipment for new automotive test systems. Yet, the architecture for proper data storage and management of the mounds of data these systems produce is often times an afterthought. Although data management may not appear as an obstacle during initial design, as the system expands, changes, and interfaces with other systems, the ability to easily access and exchange technical data becomes a critical challenge to overcome. This paper will introduce new technologies giving engineers the power to search and mine data sets to find key information and trends in the data for to rapidly turn the raw data into results.

FlexRay is a new networking protocol for embedded electronics. Technology using FlexRay provides improved throughput, determinism, and redundancy relative to existing designs using the Controller Area Network (CAN) protocol. Two criticisms of FlexRay are its increased cost and complexity compared to CAN. Although the cost will be reduced over time as usage goes up, the complexity issue is a problem of perception to some extent. This paper presents an example network design for CAN, and then adds network frames such that the throughput of CAN is exceeded. Next the paper describes how the example network design can be transitioned to FlexRay. The transition applies design practices used with CAN to reduce the complexity of FlexRay.

In many measurement applications, there is a need to correlate data acquired from different systems or synchronize systems together with precise timing. Signal Based and Time Based are the two basic methods of synchronizing instrumentation. In Signal Based synchronization, clocks and triggers are physically connected between systems. Typically this provides the highest precision synchronization. In many NVH applications size and distance constrains physically connecting the systems needed for making measurements though the inter-channel phase information of simultaneously sampled signals is crucial. In Time Based synchronization, system components have a common reference of what time it is. Events, triggers and clocks can be generated based on this time.

Several advanced signal processing algorithms beyond the FFT such as time-frequency analysis, quefrency, cestrum, wavelet analysis, and AR modeling uses are outlined. These advanced algorithms can solve some sound and vibration challenges that FFT-based algorithms cannot solve. Looking at signal characteristics of a unit under test in the time-frequency plane, it is possible to get a better understanding of signal characteristics. This is an overview of these algorithms and some application examples, such as speaker testing, bearing fault detection, dashboard motor testing, and engine knock detection where they can be applied to NVH applications.

Hardware-in-the-loop (HIL) simulation has become standard practice in the verification process of electronic control units (ECUs). However, new system control concepts continue to drive and expand the requirements for HIL systems. In this maturing application space, there is a natural trend towards the use of commercial-off-the-shelf (COTS) tools and open, multivendor hardware architectures. This open architecture is critical in helping HIL testers meet these requirements in an increasingly cost effective and higher performance manner. Multicore processors today offer performance and flexibility on a scalable computing platform, which furthers this COTS trend. Computer platforms like desktop PCs, CompactPCI and PXI [ 1 ] (CompactPCI eXtensions for Instrumentation) deliver high-performance systems that allow for the leveraging of multicore processor capabilities in achieving highly realistic plant simulations for controller testing.

ECU designers are seeking more flexibility from HIL test systems. Often their needs are met by the development of custom hardware, either internally or by HIL test system vendors. Many systems also rely heavily on the use of multiple expensive microprocessors to achieve the required timing and synchronization performance. This paper discusses an alternative based on PC technology and reconfigurable I/O hardware. The HIL test system designer uses a graphical programming interface to reconfigure not only the real-time software portion of the system, but also the FPGA-based I/O hardware. This increases flexibility and lowers cost by providing capabilities such as generating simulated outputs synchronized to crank angle and implementing multiple serial communication protocols.

With the abundance of electronic devices and sensors in automotive technology, it has become increasingly important to establish efficient, cost-effective device validation methods for CAN, J1939, and GMLAN. An easy method of validation is simultaneous sampling of multiple measurements for comparison. For instance, if you have an ECU that receives inputs using CAN, and controls analog outputs, you can measure both CAN and analog data to verify that the ECU algorithm is behaving properly. This paper will discuss techniques for sharing timing and triggering signals between CAN, analog, and digital hardware to prevent clock drift and start latencies and reduce operating system jitter. We will cover techniques to use a common clock to drive multiple boards and specify events to trigger multiple board acquisitions. Timing and triggering signals can be shared in a PC through timing and triggering cables or in PXI through the PXI Trigger bus in the backplane.

The increase in the number of electronic control units (ECUs) in the modern vehicle, combined with increased software complexity and more distributed controls has led to an extreme testing challenge when it comes to the verification and validation of body-control ECUs. In general test engineers have to deal with more software configurations, more closed-loop interaction between ECUs, and more fault conditions than ever before. By adding Unified Diagnostic Services (UDS) over CAN to a Hardware-In-The-Loop (HIL) test system, Lear was able to increase test automation and provide wider test coverage by automating the ECU flashing process, adding diagnostic identifiers and trouble codes to their test scripts, and providing a quick and easy way to exercise ECU I/O. Lear chose to implement their HIL testers on the open PXI[1] hardware platform, utilizing National Instruments' VeriStand software framework.

Vehicle communication networks are challenged by increasing demands for bandwidth, safety, and security. New data is coming into the vehicle from personal devices (e.g. mobile phones), infotainment systems, camera-based driver assistance, and wireless communication with other vehicles and infrastructure. Ethernet (IEEE 802.3) provides high levels of bandwidth and security, making it a potential solution to the challenges of vehicle communication networks. However, in order to be used in control applications, Ethernet must provide known timing performance (e.g. bounded latency and jitter), and in some cases redundancy. This paper explores use of Ethernet for in-vehicle control applications.

This is an overview of the development of a portable, real-time acoustic beamformer based on FPGA (Field Programmable Gate Arrays) and digital microphones for noise source identification. Microphone arrays can be a useful tool in identifying noise sources and give designers an image of noise distribution. The beamforming algorithm is a classic and efficient algorithm for signal processing of microphone arrays and is the core of many microphone array systems. High-speed real-time beamforming has not been implemented much in a portable instrument because it requires large computational resources. Utilizing a beamforming algorithm running on a Field Programmable Gate Array (FPGA), this camera is able to detect and locate both stationary and moving noise sources. A high-resolution optical camera located in the middle of the device records images at a rate of 25 frames per second. The use of the FPGA technology and digital microphones provides increased performance, reduced cost and weight.

Engine ECU testing requires sophisticated sensor simulation and event capture equipment. FPGAs are the ideal devices to address these requirements. Their high performance and high flexibility are perfectly suited to the rapidly changing test needs of today's advanced ECUs. FPGAs offer significant advantages such as parallel processing, design scalability, ultra-fast pin-to-pin response time, design portability, and lifetime upgradability. All of these benefits are highly valuable when validating constantly bigger embedded software in shorter duration. This paper discusses the collaboration between Valeo and NI to define, implement, and deploy a graphical, open-source, FPGA-based engine simulation library for ECU verification.